80321

Intel® 80321 I/O Processor Datasheet Product Features s s s s Core Features — Integrated Intel® XScale™ Core — ARM* V5T Instruction Set — ARM V5E DSP Extensions — 400 MHz and 600 MHz — Write Buffer, Write-back Cache PCI Bus Interface — PCI Local Bus Specification, Rev. 2.2 compliant — PCI-X Addendum to the PCI Local Bus Specification, Rev. 1.0a — 64-bit/66MHz Operation in PCI Mode —64-bit/133MHz Operation in PCI-X Mode — Support 32-bit PCI Initiators and Targets — Four Split Read Requests as Initiator — Eight Split Read Requests as Target — 64-bit Addressing Support Memory Controller —PC200 Double Data Rate (DDR) SDRAM — Up to 1 GB of 64-bit DDR SDRAM — Up to 512 MB of 32-bit DDR SDRAM — Single-bit Error Correction, Multi-bit Support (ECC) — 1024-byte Posted Memory Write Queue — 40- and 72-bit wide Memory Interface Address Translation Unit — 2 KB or 4 KB Outbound Read Queue — 4 KB Outbound Write Queue — 4 KB Inbound Read and Write Queue —Connects Internal Bus to PCI/PCI-X Bus s s s s s s s s DMA Controller — Two Independent Channels Connected to Internal Bus — Up to 1064 MB/s Burst Support in PCI-X Mode — Up to 1600 MB/s Burst Support for Internal Bus — Two 1-KB Queues in Ch-0 and Ch-1 — 232 Addressing Range on Internal Bus Interface — 264 Addressing Range on PCI Interface Application Accelerator Unit — Performs XOR on Read Data — Compute Parity Across Local Memory Blocks — 1 KB/512-byte Store Queue I2C Bus Interface Units — Two Separate I2C Units — Serial Bus — ...