74F841

74F841 10-Bit Transparent Latch March 1988 Revised August 1999 74F841 10-Bit Transparent Latch General Description The 74F841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The 74F841 is a 10-bit transparent latch, a 10-bit version of the 74F373. Features s 3-STATE output Ordering Code: Order Number 74F841SC 74F841SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009599 www.fairchildsemi.com 74F841 Unit Loading/Fan Out Pin Names D0–D9 O0–O9 OE LE Description Data Inputs 3-STATE Outputs Output Enable Input Latch Enable U.L. HIGH/LOW 1.0/1.0 150/40 1.0/1.0 1.0/1.0 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −3 mA/24 mA 20 µA/−0.6 mA 20 µA/−0.6 mA Functional Description The 74F841 device consists of ten D-type latches with 3STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data ap...