74F524

74F524 8-Bit Registered Comparator April 1988 Revised August 1999 74F524 8-Bit Registered Comparator General Description The 74F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines (S0, S1) to execute shift, load, hold and read out. An 8-bit comparator examines the data stored in the registers and on the data bus. Three true-HIGH, open-collector outputs representing “register equal to bus”, “register greater than bus” and “register less than bus” are provided. These outputs can be disabled to the OFF state by the use of Status Enable (SE). A mode control has also been provided to allow twos complement as well as magnitude compare. Linking inputs are provided for expansion to longer words. Features s 8-Bit bidirectional register with bus-oriented input-output s Independent serial input-output to register s Register bus comparator with “equal to”, “greater than” and “less than” outputs s Cascadable in groups of eight bits s Open-collector expansion comparator outputs for AND-wired s Twos complement or magnitude compare Ordering Code: Order Number 74F524SC 74F524PC Package Number M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device...