Document
74F381 4-Bit Arithmetic Logic Unit
May 1988 Revised August 1999
74F381 4-Bit Arithmetic Logic Unit
General Description
The 74F381 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional select input codes force the function outputs LOW or HIGH. Carry propagate and generate outputs are provided for use with the 74F182 carry lookahead generator for high-speed expansion to longer word lengths. For ripple expansion, refer to the 74F382 ALU data sheet.
Features
s Low input loading minimizes drive requirements s Performs six arithmetic and logic functions s Selectable LOW (clear) and HIGH (preset) functions s Carry generate and propagate outputs for use with carry lookahead generator
Ordering Code:
Order Number 74F381SC 74F381SJ 74F381PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009528
www.fairchildsemi.com
74F381
Unit Loading/Fan Out
Pin Names A0–A3 B0–B3 S0–S2 Cn G P F0–F3 Description A Operand Inputs B Operand Inputs Function Select Inputs Carry Input Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Function Outputs U.L. HIGH/LOW 1.0/3.0 1.0/3.0 1.0/1.0 1.0/4.0 50/33.3 50/33.3 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/−1.8 mA 20 µA/−1.8 mA 20 µA/−0.6 mA 20 µA/−2.4 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA
Functional Description
Signals applied to the Select inputs S0–S2 determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arithmetic functions for either active HIGH or active LOW operands, with output levels in the same convention. In the Subtract operating modes, it is necessary to force a carry (HIGH for active HIGH operands, LOW for active LOW operands) into the Cn input of the least significant package. The Carry Generate (G) and Carry Propagate (P) outputs supply input signals to the 74F182 carry lookahead generator for expansion to longer word length, as shown in Figure 2. Note that an 74F382 ALU is used for the most significant package. Typical delays for Figure 2 are given in Figure 1.
Function Select Table
Select S0 L H L H L H L H
H = HIGH Voltage Level L = LOW Voltage Level
S1 L L H H L L H H
S2 L L L L H H H H
Operation Clear B Minus A A Minus B A Plus B A⊕ B A+B AB Preset
Toward Path Segment F Ai or Bi to P Pi to Cn + ('F182) Cn to F Cn or Cn + 4, OVR Total Delay 7.2 ns 6.2 ns 8.1 ns — 21.5 ns
Output Cn + 4, OVR 7.2 ns 6.2 ns — 8.0 ns 21.4 ns
FIGURE 1. 16-Bit Delay Tabulation
FIGURE 2. 16-Bit Lookahead Carry ALU Expansion
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