74F377A

INTEGRATED CIRCUITS 74F377A Octal D-type flip-flop with enable Product specification IC15 Data Handbook 1996 Mar 12 Philips Semiconductors Philips Semiconductors Product specification Octal D-type flip-flop with enable 74F377A FEATURES High states) High impedance inputs for reduced loading (20µA in Low and Ideal for addressable register applications Enable for address and data synchronization applications Eight edge–triggered D–type flip–flops Buffered common clock See ’F273A for Master Reset version See ’F373 for transparent latch version See ’F374 for 3–State version TYPE 74F377A TYPICAL fMAX 165MHz DESCRIPTION The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation. TYPICAL SUPPLY CURRENT (TOTAL) 29mA ORDERING INFORMATION PACKAGES 20–pin plastic DIP 20–pin plastic SOL COMMERCIAL RANGE VCC = 5V±10%; Tamb = 0°C to +70°C N74F377AN N74F377AD PKG. DWG. # SOT146-1 SOT163-1 INPUT AND OUTPUT LOADING AND FAN–OUT TABLE PINS D0 – D7 CP E Q0 – Q7 Data inputs Clock pulse input (active rising edge) Enable input (active–Low) Data output...