74F280

54F 74F280 9-Bit Parity Generator Checker August 1995 54F 74F280 9-Bit Parity Generator Checker General Description The ’F280 is a high-speed parity generator checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH If an even number of inputs is HIGH the Sum Even output is HIGH If an odd number is HIGH the Sum Even output is LOW The Sum Odd output is the complement of the Sum Even output Features Y Guaranteed 4000V minimum ESD protection Commercial 74F280PC Military Package Number N14A Package Description 14-Lead (0 300 Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0 150 Wide) Molded Small Outline JEDEC 14-Lead (0 300 Wide) Molded Small Outline EIAJ 14-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F280DM (Note 2) 74F280SC (Note 1) 74F280SJ (Note 1) 54F280FM (Note 2) 54F280LM (Note 2) J14A M14A M14D W14B E20A Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9512–3 IEEE IEC TL F 9512 – 1 TL F 9512 – 2 TL F 9512–5 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9512 RRD-B30M115 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 50 33 3 50 33 3 Inpu...