Document
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS™ transistor
FEATURES
• ’Trench’ technology • Very low on-state resistance • Fast switching • Logic level compatible
g
PSMN010-55D
QUICK REFERENCE DATA
SYMBOL
d
VDSS = 55 V ID = 75 A RDS(ON) ≤ 10.5 mΩ (VGS = 10 V) RDS(ON) ≤ 12 mΩ (VGS = 5 V)
s
GENERAL DESCRIPTION
SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:• d.c. to d.c. converters • switched mode power supplies The PSMN010-55D is supplied in the SOT428 (Dpak) surface mounting package.
PINNING
PIN 1 2 3 tab gate drain1 source DESCRIPTION
SOT428 (DPAK)
tab
2
drain
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Continuous gate-source voltage Peak pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tj ≤ 150 ˚C Tmb = 25 ˚C; VGS = 5 V Tmb = 100 ˚C; VGS = 5 V Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 55 55 ± 15 ± 20 752 57 240 125 175 UNIT V V V V A A A W ˚C
1 It is not possible to make connection to pin 2 of the SOT428 package. 2 Continuous current rating limited by package. October 1999 1 Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS™ transistor
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS IAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 74 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω; VGS = 5 V MIN. -
PSMN010-55D
MAX. 264 75
UNIT mJ A
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT428 package, pcb mounted, minimum footprint TYP. MAX. UNIT 50 1.2 K/W K/W
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 4.5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175˚C Gate source leakage current VGS = ±10 V; VDS = 0 V Zero gate voltage drain VDS = 25 V; VGS = 0 V; current Tj = 175˚C Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 75 A; VDD = 44 V; VGS = 5 V MIN. 55 42 1 0.5 TYP. MAX. UNIT 1.5 7.4 8.6 9.1 0.02 0.05 55 13 28 19 114 250 216 3.5 7.5 3300 560 370 2 2.3 10.5 12 13 25 100 10 500 V V V V V mΩ mΩ mΩ mΩ nA µA µA nC nC nC ns ns ns ns nH nH pF pF pF
IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss
VDD = 30 V; RD = 1.2 Ω; VGS = 10 V; RG = 10 Ω Resistive load Measured tab to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 20 V; f = 1 MHz
October 1999
2
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS™ transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 25 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V -
PSMN010-55D
TYP. MAX. UNIT 0.95 70 0.16 75 240 1.2 A A V ns µC
October 1999
3
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS™ transistor
PSMN010-55D
Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
10
Transient thermal impedance, Zth j-mb (K/W)
1 0.2 0.1 0.1 0.05 0.02 0.01
D = 0.5
P D
tp
D = tp/T
single pulse T 0.001 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00
Pulse width, tp (s)
Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
Drain Current, ID (A) VGS = 10V 5V 3V 2.8 V
Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
50 45 40 35 30 25 20 15 10 5 0 0
Tj = 25 C 2.6 V
2.4 V
2.2 V 2V
0.2
0.4
0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V)
1.6
1.8
2
Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID
Fig.5. Typical output.