Dual N & P-Channel Enhancement Mode Field Effect Transistor
These dual N- and P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications such
as notebook computer power management, Half bridge motor
control, cellular phone, and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
N-Channel 3.5A, 20V, RDS(ON) = 0.1Ω @ VGS = 10V.
P-Channel -3.5A , -20V, RDS(ON) = 0.1Ω @ VGS = -10V.
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
Absolute Maximum Ratings
TA = 25°C unless otherwise noted
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current - Continuous TA = 25°C
- Continuous TA = 70°C
- Pulsed TA = 25°C
PD Power Dissipation for Dual Operation
Power Dissipation for Single Operation
TJ,TSTG Operating and Storage Temperature Range
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
-55 to 150
© 1997 Fairchild Semiconductor Corporation