Dual P-Channel Enhancement Mode Field Effect Transistor
This P-Channel enhancement mode power field ef-
fect transistor is produced using Fairchild’s propri-
etary, high cell density, DMOS technology. This very
high density process is especially tailored to mini-
mize on-state resistance and provide superior
These devices are particularly suited for low voltage
apllications such as DC motor control and DC/
DC conversion where fast switching,low in-line
power loss, and resistance to transients are
• -2.8 A, -20 V. RDS(on) = 0.14 Ω @ VGS = -4.5 V
RDS(on) = 0.19 Ω @ VGS = -2.7 V
RDS(on) = 0.20 Ω @ VGS = -2.5 V.
• High density cell design for extremely low RDS(on).
• High power and current handling capability in a
widely used surface mount package.
• Dual MOSFET in surface mount package.
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Drain Current - Continuous
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
Package Outlines and Ordering Information
©1999 Fairchild Semiconductor Corporation
-55 to +150
NDS9933A Rev. A