P-Channel Logic Level Enhancement Mode Field Effect Transistor
SuperSOTTM-3 P-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications such as notebook computer power management,
portable electronics, and other battery powered circuits where
fast high-side switching, and low in-line power loss are
needed in a very small outline surface mount package.
-1.1 A, -30 V, RDS(ON) = 0.3 Ω @ VGS=-4.5 V
RDS(ON) = 0.2 Ω @ VGS=-10 V.
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
Absolute Maximum Ratings
TA = 25°C unless otherwise noted
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
PD Maximum Power Dissipation
TJ,TSTG Operating and Storage Temperature Range
Thermal Resistance, Junction-to-Ambient (Note 1a)
Thermal Resistance, Junction-to-Case
-55 to 150
© 1997 Fairchild Semiconductor Corporation