July 1996
NDC631N N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel l...
July 1996
NDC631N N-Channel Logic Level Enhancement Mode Field Effect
Transistor
General Description
These N-Channel logic level enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.
Features
4.1 A, 20 V. RDS(ON) = 0.06 Ω @ VGS = 4.5 V RDS(ON) = 0.075 Ω @ VGS =2.7 V. Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability.
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4
3
5
2
6
1
Absolute Maximum Ratings T A = 25°C unless otherwise note
Symbol Parameter VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed Maximum Power Dissipation
(Note 1a) (Note 1b) (Note 1c) (Note 1a)
NDC631N 20 8 4.1 15 1.6 1 0.8 -55 to 150
Units V V A
W
TJ,TSTG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note...