NBSG16MMNR2

NBSG16M 2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer The NBSG16M is a differential current mode logic (CML) receiver/driver/translator buffer. The device is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities. Inputs incorporate internal 50 W termination resistors and accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The CML output structure contains internal 50 W source termination resistor to VCC. The device generates 400 mV output amplitude with 50 W receiver resistor to VCC. The VBB pin is internally generated voltage supply available to this device only. For all single−ended input conditions, the unused complementary differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open. http://onsemi.com MARKING DIAGRAM* QFN−16 MN SUFFIX CASE 485G A L Y W SG 16M ALYW = Assembly Location = Wafer Lot = Year = Work Week *For additional marking information, refer to Application Note AND8002/D. Maximum Input Clock Frequency > 10 GHz Typical Maximum Input Data Rate > 10 Gb/s Typical 120 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Negative CML Output with...