PM8351

PMC-Sierra,Inc. PM8351 OctalPHY™ 8-Channel 1.0-1.25 Gbps Transceiver FEATURES Eight independent 1.0-1.25 Gbit/s transceivers Ultra low power operation: 1.25 Watts typical Integrated serializer/deserializer, clock synthesis, clock recovery, and 8B/10B encode/decode logic Physical Coding Sublayer (PCS) logic for Gigabit Ethernet Optional receive FIFO which synchronizes incoming data to local clock domain Dual Data Rate (DDR) parallel interface with clock forwarding to halve ASIC terminal count and simplify timing Extensive control of loopback, BIST, and operating modes via 802.3 compliant MDC/MDIO serial interface Built-in packet generator/checker “Trunking” feature to de-skew and align received parallel data across eight channels IEEE 1149.1 JTAG testing support IEEE 802.3z Gigabit Ethernet and ANSI X3T11 FibreChannel support High speed outputs which feature programmable output current to directly drive dual-terminated line 2.5 V, 0.25 µ CMOS technology with 3.3V tolerant I/O Direct interface to optical modules, coax, or serial backplanes Small footprint 19x19 mm, 289-pin PBGA APPLICATIONS High speed serial backplanes Gigabit Ethernet links FibreChannel links Intra-system interconnect ASIC to PMD link EXAMPLE ARCHITECTURE The first figure on the next page shows the OctalPHY in a switch application. This implementation uses eight channels of 1.25 Gbaud per linecard, requiring only 32 signal pins per linecard and 128 for the switch car...