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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MMBTA63LT1/D
Darlington Transistors
PNP Silicon
COLLECTOR 3 BASE 1
MMBTA63LT1 MMBTA64LT1*
*Motorola Preferred Device
EMITTER 2
3
MAXIMUM RATINGS
Rating Collector – Emitter Voltage Collector – Base Voltage Emitter – Base Voltage Collector Current — Continuous Symbol VCES VCBO VEBO IC Value –30 –30 –10 –500 Unit Vdc Vdc Vdc mAdc
1 2
CASE 318 – 08, STYLE 6 SOT– 23 (TO – 236AB)
DEVICE MARKING
MMBTA63LT1 = 2U; MMBTA64LT1 = 2V
THERMAL CHARACTERISTICS
Characteristic Total Device Dissipation FR–5 Board,(1) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Total Device Dissipation Alumina Substrate,(2) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Junction and Storage Temperature Symbol PD Max 225 1.8 RqJA PD 556 300 2.4 RqJA TJ, Tstg Characteristic Symbol 417 –55 to +150 Unit mW mW/°C °C/W mW mW/°C °C/W °C
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Min Max Unit
OFF CHARACTERISTICS
Collector – Emitter Breakdown Voltage (IC = –100 µAdc) Collector Cutoff Current (VCB = –30 Vdc) Emitter Cutoff Current (VEB = –10 Vdc) V(BR)CEO ICBO IEBO hFE MMBTA63 MMBTA64 MMBTA63 MMBTA64 VCE(sat) VBE(on) fT 5,000 10,000 10,000 20,000 — — — — — — –1.5 –2.0 Vdc Vdc –30 — — — –100 –100 Vdc nAdc nAdc
ON CHARACTERISTICS
DC Current Gain(3) (IC = –10 mAdc, VCE = –5.0 Vdc) (IC = –10 mAdc, VCE = –5.0 Vdc) (IC = –100 mAdc, VCE = –5.0 Vdc) (IC = –100 mAdc, VCE = –5.0 Vdc) —
Collector – Emitter Saturation Voltage (IC = –100 mAdc, IB = –0.1 mAdc) Base–Emitter On Voltage (IC = –100 mAdc, VCE = –5.0 Vdc)
SMALL– SIGNAL CHARACTERISTICS
Current – Gain — Bandwidth Product (IC = –10 mAdc, VCE = –5.0 Vdc, f = 100 MHz) 1. FR–5 = 1.0 x 0.75 x 0.062 in. 2. Alumina = 0.4 x 0.3 x 0.024 in. 99.5% alumina. 3. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%. Thermal Clad is a trademark of the Bergquist Company
Preferred devices are Motorola recommended choices for future use and best overall value.
125
—
MHz
Motorola Small–Signal Transistors, FETs and Diodes Device Data © Motorola, Inc. 1996
1
MMBTA63LT1 MMBTA64LT1
200 hFE , DC CURRENT GAIN (X1.0 K) 100 70 50 30 20 10 7.0 5.0 3.0 2.0 –0.3 25°C VCE = –2.0 V –5.0 V –10 V TA = 125°C
–55°C
–0.5
–0.7
–1.0
–2.0
–3.0
–5.0
–7.0
–10
–20
–30
–50
–70
–100
–200
–300
IC, COLLECTOR CURRENT (mA)
Figure 1. DC Current Gain
–2.0 TA = 25°C –1.6 V, VOLTAGE (VOLTS) VBE(sat) @ IC/IB = 100
VCE , COLLECTOR–EMITTER VOLTAGE (VOLTS)
–2.0 –1.8 –1.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.1–0.2 –0.5 –1 –2 IC = –10 mA –50 mA –100 mA –175 mA
TA = 25°C
–1.2 VBE(on) @ VCE = –5.0 V –0.8 VCE(sat) @ IC/IB = 1000 IC/IB = 100 –0.4
–300 mA
0 –0.3 –0.5
–1.0
–2 –3 –5 –10 –20 –30 –50 IC, COLLECTOR CURRENT (mA)
–100 –200 –300
–5 –10 –20 –50 –100–200–500 –1K–2K –5K–10K IB, BASE CURRENT (µA)
Figure 2. “On” Voltage
Figure 3. Collector Saturation Region
10 |h FE |, HIGH FREQUENCY CURRENT GAIN VCE = –5.0 V f = 100 MHz TA = 25°C
4.0 3.0 2.0 1.0 0.4 0.2
0.1 –1.0 –2.0
–5.0
–10
–20
–50
–100 –200
–500
–1K
IC, COLLECTOR CURRENT (mA)
Figure 4. High Frequency Current Gain
2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
MMBTA63LT1 MMBTA64LT1
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95
0.037 0.95
0.079 2.0 0.035 0.9 0.031 0.8
inches mm
SOT–23 SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by T J(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA . Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = TJ(max) – TA RθJA
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the di.