MM74C48

MM74C48 BCD-to-7 Segment Decoder October 1987 Revised January 1999 MM74C48 BCD-to-7 Segment Decoder General Description The MM74C48 BCD-to-7 segment decoder is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. Seven NAND gates and one driver are connected in pairs to make binary-coded decimal (BCD) data and its complement available to the seven decoding AND-OR-INVERT gates. The remaining NAND gate and three input buffers provide test-blanking input/ripple-blanking output, and ripple-blanking inputs. Features s Wide supply voltage range: s Guaranteed noise margin: s High noise immunity: fan out of 2 driving 74L s High current sourcing output (up to 50 mA) s Ripple blanking for leading or trailing zeros (optional) s Lamp test provision 3.0V to 15V 1.0V 0.45 VCC (typ.) s Low power TTL compatibility: Ordering Code: Order Number MM74C48N Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Connection Diagrams Pin Assignments for DIP Segment Identification Numerical Designations and Resultant Displays Top View © 1999 Fairchild Semiconductor Corporation DS005883.prf www.fairchildsemi.com MM74C48 Truth Table Decimal or Function 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT H = HIGH Level L = LOW Level X = Irrelevant Note 1: One BI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). Note 2: The blanking input (...