ML6692

April 1999 ML6692 100BASE-TX Physical Layer with MII GENERAL DESCRIPTION The ML6692 implements the complete physical layer of the Fast Ethernet 100BASE-TX standard. The ML6692 interfaces to the controller through the standard-compliant Media Independent Interface (MII). The ML6692 functionality includes auto-negotiation, 4B/5B encoding/ decoding, Stream Cipher scrambling/descrambling, 125MHz clock recovery/generation, receive adaptive equalization, baseline wander correction, and MLT-3/ 10BASE-T transmitter. For applications requiring 100Mbps only, such as repeaters, the ML6692 offers a single-chip per-port solution. For 10/100 dual speed adapters or switchers, 10BASE-T functionality may be attained using Micro Linear’s ML2653, or by using an Ethernet controller that contains an integrated 10BASE-T PHY. FEATURES s s s s Single-chip 100BASE-TX physical layer Compliant to IEEE 802.3u 100BASE-TX standard Supports adapter, repeater and switch applications Single-jack 10BASE-T/100BASE-TX solution when used with external 10Mbps PHY Compliant MII (Media Independant Interface) Auto-negotiation capability 4B/5B encoder/decoder Stream Cipher scrambler/descrambler 125MHz clock recovery/generation Baseline wander correction Adaptive equalization and MLT-3 encoding/decoding Supports full-duplex operation s s s s s s s s BLOCK DIAGRAM 1 9 (PLCC Package) 49 48 CLOCK SYNTHESIZER TXCLK 3 4 5 6 7 8 18 19 17 10 12 14 16 21 23 24 25 TXD3 TXD2 TXD1 TXD0 TXEN TXER CRS COL RXCLK RXD3 RXD2...