Document
January 1997
ML4622, ML4624
Fiber Optic Data Quantizer
GENERAL DESCRIPTION
The ML4622 and ML4624 data quantizers are low noise, wideband, bipolar monolithic ICs designed specifically for signal recovery applications in fiberoptic receiver systems. They contain a wideband limiting amplifier which is capable of accepting an input signal as low as 2mVP-P with a 55dB dynamic range. This high level of sensitivity is achieved by using a DC restoration feedback loop which nulls any offset voltage produced in the limiting amplifier. The output stage is a high speed comparator circuit with both TTL and ECL outputs. An enable pin is included for added control. The Link Detect circuit provides a Link Monitor function with a user selectable reference voltage. This circuit monitors the peaks of the input signal and provides a logic level output indicating when the input falls below an acceptable level. This output can be used to disable the quantizer and/or drive an LED, providing a visible link status.
FEATURES
Data rates up to 40MHz or 80MBd Can be powered by either +5V providing TTL or raised ECL level outputs or –5.2V providing ECL levels s Low noise design: 25µV RMS over bandwidth s Adjustable Link Monitor function with hystersis s Wide 55dB input dynamic range s Low power design s ML4624 is pin compatible with the ML4621
s s
APPLICATIONS
s s s
IEEE 802.3 10BASE-FL Receiver IEEE 802.5 fiber optic token ring, 4 and 16mbps Fiber Optic Data Communications and Telecommunications Receivers
ML4622/ML4624 BLOCK DIAGRAM
CF1 BIAS
CF2
ECL+
ECL–
VIN+ AMP VIN–
ECL CMP
TTL CMP
TTL OUT
CMP ENABLE
∫
VDC VCC TTL* VCC GND VREF REF GND TTL
VTHADJ
THRESH GEN
LINK DETECT
TTL LINK MON
CTIMER *ML4624 ONLY
1
ML4622, ML4624
PIN CONNECTIONS
ML4622 16-Pin DIP or SOIC (Narrow) ML4624 24-Pin Narrow DIP ML4624 28-Pin PCC
NC TTL LINK MON TTL LINK MON GND VIN– VIN+ VDC CF2 CF1 GND TTL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CMP ENABLE VTHADJ VREF CTIMER VCC TTL OUT ECL+ ECL– CMP ENABLE VIN– VIN+ VDC CF2 CF1 NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC NC NC CTIMER VREF VTHADJ GND TTL OUT VCC TTL GND TTL ECL+ ECL– VIN– VIN+ NC VDC CF2 CF1 NC
CMP ENABLE NC 4 5 6 7 8 9 10 11 12 13 3
TTL LINK MON NC VCC NC NC 2 1 28 27 26 25 24 23 22 21 20 14 15 16 19 17 18 ECL+ ECL– GND TTL NC CTIMER VREF VTHADJ GND TTL OUT VCC TTL
TOP VIEW
NC NC NC NC
TOP VIEW
2
ML4622, ML4624
PIN DESCRIPTION
NAME TTL LINK MON FUNCTION TTL Link Monitor output. Signal is low when the VIN+, VIN– inputs exceed the minimum threshold, which is set by a voltage on the VTH ADJ pin. Signal is high when the input signal level is below the threshold. Capable of driving a 10mA LED indicator. This pin can be tied to CMP ENABLE. A low voltage at this TTL input pin enables both the ECL and the TTL outputs. A high TTL voltage disables the comparator output with ECL+ high, ECL– low, and TTL OUT high. This input pin should be capacitively coupled to the input source or to filtered ground. (The input resistance is approximately 1.6kΩ.) This input pin should be capacitively coupled to the input source or to filtered ground. (The input resistance is approximately 1.6kΩ.) The ECL comparator negative output. Has internal pull down resistor. External pull downs are not required unless driving a large capacitive load. The ECL comparator positive output. Has internal pull down resistor. External pull downs are not required unless driving a large capacitive load. The negative supply for the TTL comparator stage. If the TTL output is not necessary, connect GND TTL to VCC. NAME VCC TTL FUNCTION The positive supply for the TTL comparator stage. If the TTL output is not necessary, connect VCC TTL to VCC . (ML4624 only) TTL data output. An external capacitor on this pin integrates an error signal which nulls the offset of the input amplifier. If the DC feedback loop is not being used, this pin should be connected to VREF. A capacitor from this pin to CF1 controls the maximum bandwidth of the amplifier. Connect to CF2 through a capacitor. Negative supply. Connect to –5.2V for ECL operation, or to ground for TTL or raised ECL operation. This input pin sets the link monitor threshold. A 2.5V reference with respect to GND. A capacitor from this pin to VCC determines the Link Monitor response time. Positive supply. Connect to ground for negative ECL operation, or to 5V for TTL or raised ECL operation.
TTL OUT VDC
CMP ENABLE
CF2
VIN–
CF1 GND
VIN+
V THADJ V REF CTIMER
ECL–
ECL+
VCC
GND TTL
3
ML4622, ML4624
ABSOLUTE MAXIMUM RATINGS
VCC – GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0 VCC TTL – GND TTL . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0 Inputs/Outputs GND . . . . . . . . . . . . . . . . . . . –0.3 to VCC +0.3 Storage Temperature Range . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering 10 sec.) . . . . . . . . . . . . . . +260°C
ML4622, ML4624 ELECTRICAL CHARACTERISTIC.