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MK50H28 Dataheets PDF



Part Number MK50H28
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description MULTI LOGICAL LINK FRAME RELAY CONTROLLER
Datasheet MK50H28 DatasheetMK50H28 Datasheet (PDF)

® MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits(PVCs). Optional Transparent Mode (no LMI Protocol Processing - all frame data received). Local Management Link Protocol with optional Bi-directional message processing. Detects and indicates service-affecting errors in the timing or content of events. Programmable Timers/Counters: nT1/T39.

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® MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits(PVCs). Optional Transparent Mode (no LMI Protocol Processing - all frame data received). Local Management Link Protocol with optional Bi-directional message processing. Detects and indicates service-affecting errors in the timing or content of events. Programmable Timers/Counters: nT1/T391, nT2/T392, nN1/N391, nN2/N392, nN3/N393 and dN1 for the LMI/LIV channel. Provides Error Counters for the LMI channel and Congestion Statistics for all the active channels. LMI/LIV Frames can be transmitted/received on DLCI 0 or 1023. Supports reception of up to 4 octets of address field with a maximum of 8192 active channels or DLCIs (Data Link Connection Identifiers) Priority DLCI scheme for channels requiring higher rate of service. Buffer Management includes: - Initialization Block - Address Look Up Table - Context Table - Separate Receive and Transmit Rings of variable size for each active channel On chip DMA control with programmable burst length. Handles all HDLC frame formatting: - Zero bit insertion and deletion - FCS (CRC) generation and detection - Frame delimiting with flags Programmable minimum frame spacing on transmission (1-62 flags between frames). Selectable FCS (CRC) of 16 or 32 bits. Testing Facilities: Internal Loopback, Silent Loopback, Clockless Loopback, and Self Test. System clock rates up to 25 MHz. CMOS process; Fully compatible with both 8 and 16 bit systems; All inputs and outputs are TTL compatible. Programmable for full or half duplex operation. March 2000 DIP48 PLCC52 Pin-for-pin compatible and architecturally the same as the MK50H25 (X.25/LAPD) and MK50H27 (CCS#7). SECTION 2 - DESCRIPTION The STMicroelectronics MK50H28 Multi-Logical Link Communications Controller is a CMOS VLSI device which provides link level data communications control for Frame Relay Applications on Permanent Virtual Circuits (PVCs). The MK50H28 will perform frame formating including: frame delimiting with flags, transparency (so-called ”bitstuffing”), plus FCS (CRC) generation and detection. It also supports Local Management Interface (LMI) protocol with the ”Optional Bidirectional Procedures” (Annex D, T1.617 - 1991 and T1.617a1994). One of the outstanding features of the MK50H28 is its buffer management which includes on-chip dual channel DMA. This feature allows users to receive and transmit multiple data frames at a time. (A conventional serial communications control chip plus a separate DMA chip would handle data for only a single block at a time.) The 1/64 MK50H28 DESCRIPTION (Continued) MK50H28 will move multiple blocks of receive and transmit data directly into and out of memory through the Host’s bus. Moreover, the memory management capability includes the chaining of long frames. A possible system configuration for the MK50H28 is shown in Figure 1. The MK50H28 may be used with any of several popular 16 and 8 bit microprocessors, such as 68000, 6800, Z8000, Z80, LSI- 11, 8086, 8088, 8080, etc. The MK50H28 may be operated in either full or half duplex mode. In half duplex mode, the RTS and CTS modem control pins are provided. In full duplex mode, these pins become user programmable I/O pins. All signal pins on the MK50H28 are TTL compatible. This has the advantage of making the MK50H28 independent of the physical interface. As shown in Figure 1, line drivers and receivers are used for electrical connection to the physical layer. DIP48 PIN CONNECTION (Top view) VSS-GND DAL07 DAL06 DAL05 DAL04 DAL03 DAL02 DAL01 DAL00 READ INTR DALI DALO DAS BMO, BYTE, BUSREL BMI, BUSAKO HOLD, BUSRQ ALE, AS HLDA CS ADR READY RESET VSS-GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 VCC (+5V) DAL08 DAL09 DAL10 DAL11 DAL12 DAL13 DAL14 DAL15 A16 A17 A18 A19 A20 A21 A22 A23 RD DSR, CTS TD SYSCLK RCLK DTR, RTS TCLK M K 5 0 H 2 8 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2/64 MK50H28 PLCC52 PIN CONNECTION (Top view) No Connect DAL03 DAL04 DAL05 DAL06 DAL07 8 7 DAL02 DAL01 DAL00 READ INTR DALI DALO DAS BMO/BYTE/BUSREL No Connect BM1/BUSAKO HOLD/BUSRQ ALE/AS GND VCC DAL08 DAL09 DAL10 DAL11 DAL12 1 52 47 46 MK50H28Q 20 21 ADR READY RESET HLDA CS GND No Connect 34 33 TCLK DTR/RTS RCLK SYSCLK TD DSR/CTS DAL13 DAL14 DAL15 A16 A17 A18 A19 A20 A21 A22 No Connect A23 RD 3/64 MK50H28 TAble 1 - PIN DESCRIPTION LEGEND: I IO OD Note: Input only Input / Output Open Drain (no internal pull-up) O 3S Output only 3-State Pin out for 52 pin PLCC is shown in brackets. PIN(S) 2-9 40-47 [2-10 44-51] 10 [11] TYPE IO/3S DESCRIPTION The time multiplexed Data/Address bus. During the address portion of a memory transfer, DAL<15:00> contains the lower 16 bits of the memory address. During the data portion of a memory transfer, DAL<15:00> contains the read or write data, depending on the t.


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