Document
I C R O C LOC K
Description
The MK3233 is the smallest size, lowest power system clock synthesizer available. It is the ideal way to generate clocks for smart cell phones, PDAs, and other devices where low power is required. Using analog Phase-Locked Loop (PLL) techniques, the device operates from a single 32.768 kHz crystal to produce the 32.768 kHz, CPU, and serial communications output clocks. The device has multiple power down modes for the CPU, communications, and 32.768 kHz clocks. The MK3233 can save board space and cost even if it only replaces the 32 kHz oscillator circuitry and one additional surface mount crystal or oscillator. The extremely low IDD, the ease of surface mounting, the upgradeability of CPU frequencies, and the power down capability are added benefits in using the part.
MK3233 Handheld System Clock Synthesizer
Features
• Input crystal frequency of 32.768 kHz • Lowest power solution available • Operating temperature of -20 to 70 °C • Output clock frequencies up to 50 MHz • Three output clocks • 3.3 V or 5.0 V operation • Duty cycle of 45/55 • Eight selectable CPU frequencies • CPU or Communication clock power down • Separate battery supply pin for 32 kHz runs to 2V • IDD less than 4µA when 32 kHz running • Serial port clocks of 1.8432 MHz (-01 version) or 3.6864 MHz (-02 version) • Packaged in 16 pin narrow SOIC
Block Diagram
VDD GND
CPUS0 CPUS1 CPUS2 PDCPU
CPU Clock Synthesis and Control Circuitry
Output Buffer
CPUCLK
PDCOMM PD VDD32 32.768 kHz crystal X1 or clock
X2
Communications Clock Synthesis and Control Circuitry
Output Buffer
1.843 or 3.686 MHz
Crystal Oscillator
Output Buffer
32.768 kHz
MDS 3233 F
1
Revision 11070
Printed 11/16/00
Integrated Circuit Systems, Inc.• 525 Race Street• San Jose • CA • 95126• (408) 295-9800 tel • www.icst.com
I C R O C LOC K
Pin Assignment
CPUS2 X2 X1 VDD32 VDD GND COMMCLK 32K 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CPUS1 CPUS0 CPUCLK VDD GND PD PDCPU
MK3233 Handheld System Clock Synthesizer
CPU Clock Decoding
CPUS2 CPUS1 CPUS0 CPUCLK (MHz) 0 0 0 8.00 0 0 1 13.00 0 1 0 16.00 0 1 1 20.00 1 0 0 40.00 1 0 1 25.00 1 1 0 50.00 1 1 1 33.33
PDCOMM
Frequency transitions will occur smoothly.
Pin Descriptions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name CPUS2 X2 X1 VDD32 VDD GND COMMCLK 32K PDCOMM PDCPU PD GND VDD CPUCLK CPUS0 CPUS1 Type I O I P P P O O I I I P P O I I Description Select 2 for CPUCLK frequencies. See Table above. Crystal connection. Connect to 32.768 kHz crystal. Crystal connection. Connect to 32.768 kHz crystal. Separate power supply connection for 32.768 kHz clock. Will operate to 2.0 V. Connect to +3.3 V or +5 V. Must be the same voltage as pin 13. Connect to ground. Serial communications (1.84 on -01 version, or 3.68MHz on -02 version) clock output. 32.768 kHz square wave clock output. Power Down serial Communications clock output (stops low) when low. Power Down CPU clock output (stops low) when low. Powers Down everything but 32 kHz oscillator i.