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80C188XL Dataheets PDF



Part Number 80C188XL
Manufacturers Intel Corporation
Logo Intel Corporation
Description 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Datasheet 80C188XL Datasheet80C188XL Datasheet (PDF)

80C186XL 80C188XL 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS Y Low Power Fully Static Versions of 80C186 80C188 Operation Modes Enhanced Mode DRAM Refresh Control Unit Power-Save Mode Direct Interface to 80C187 (80C186XL Only) Compatible Mode NMOS 80186 80188 Pin-for-Pin Replacement for Non-Numerics Applications Integrated Feature Set Static Modular CPU Clock Generator 2 Independent DMA Channels Programmable Interrupt Controller 3 Programmable 16-Bit Timers Dynamic RAM Refresh Control Unit Pro.

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80C186XL 80C188XL 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS Y Low Power Fully Static Versions of 80C186 80C188 Operation Modes Enhanced Mode DRAM Refresh Control Unit Power-Save Mode Direct Interface to 80C187 (80C186XL Only) Compatible Mode NMOS 80186 80188 Pin-for-Pin Replacement for Non-Numerics Applications Integrated Feature Set Static Modular CPU Clock Generator 2 Independent DMA Channels Programmable Interrupt Controller 3 Programmable 16-Bit Timers Dynamic RAM Refresh Control Unit Programmable Memory and Peripheral Chip Select Logic Programmable Wait State Generator Local Bus Controller Power-Save Mode System-Level Testing Support (High Impedance Test Mode) Y Y Completely Object Code Compatible with Existing 8086 8088 Software and Has 10 Additional Instructions over 8086 8088 Speed Versions Available 25 MHz (80C186XL25 80C188XL25) 20 MHz (80C186XL20 80C188XL20) 12 MHz (80C186XL12 80C188XL12) Direct Addressing Capability to 1 MByte Memory and 64 Kbyte I O Available in 68-Pin Plastic Leaded Chip Carrier (PLCC) Ceramic Pin Grid Array (PGA) Ceramic Leadless Chip Carrier (JEDEC A Package) Available in 80-Pin Quad Flat Pack (EIAJ) Shrink Quad Flat Pack (SGFP) Available in Extended Temperature Range ( b 40 C to a 85 C) Y Y Y Y Y Y The Intel 80C186XL is a Modular Core re-implementation of the 80C186 microprocessor It offers higher speed and lower power consumption than the standard 80C186 but maintains 100% clock-for-clock functional compatibility Packaging and pinout are also identical 272431-1 Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata October 1995 COPYRIGHT INTEL CORPORATION 1995 Order Number 272431-004 1 80C186XL 80C188XL 16-Bit High-Integration Embedded Processors CONTENTS INTRODUCTION 80C186XL CORE ARCHITECTURE 80C186XL Clock Generator Bus Interface Unit 80C186XL PERIPHERAL ARCHITECTURE Chip-Select Ready Generation Logic DMA Unit Timer Counter Unit Interrupt Control Unit Enhanced Mode Operation Queue-Status Mode DRAM Refresh Control Unit Power-Save Control Interface for 80C187 Math Coprocessor (80C186XL Only) ONCE Test Mode PACKAGE INFORMATION Pin Descriptions 80C186XL 80C188XL Pinout Diagrams ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings DC SPECIFICATIONS Power Supply Current PAGE 4 4 4 5 5 5 6 6 6 6 6 7 7 7 7 8 8 16 22 22 22 23 CONTENTS AC SPECIFICATIONS Major Cycle Timings (Read Cycle) Major Cycle Timings (Write Cycle) Major Cycle Timings (Interrupt Acknowledge Cycle) Software Halt Cycle Timings Clock Timings Ready Peripheral and Queue Status Timings Reset and Hold HLDA Timings AC TIMING WAVEFORMS AC CHARACTERISTICS EXPLANATION OF THE AC SYMBOLS DERATING CURVES 80C186XL 80C188XL EXPRESS 80C186XL 80C188XL EXECUTION TIMINGS INSTRUCTION SET SUMMARY REVISION HISTORY ERRATA PRODUCT IDENTIFICATION PAGE 24 24 26 27 28 29 30 31 36 37 39 40 41 41 42 48 48 48 2 2 80C186XL 80C188XL NOTE Pin names in parentheses applies to 80C188XL Figure 1 80C186XL 80C188XL Block Diagram 3 3 272431– 2 80C186XL 80C188XL (2a) 272431 – 3 272431 – 4 (2b) Note 1 XTAL Frequency L1 Value 20 MHz 12 0 mH g 20% 25 MHz 8 2 mH g 20% 32 MHz 4 7 mH g 20% 40 MHz 3 0 mH g 20% LC network is only required when using a third overtone crystal Figure 2 Oscillator Configurations (see text) INTRODUCTION Unless specifically noted all references to the 80C186XL apply to the 80C188XL References to pins that differ between the 80C186XL and the 80C188XL are given in parentheses The following Functional Description describes the base architecture of the 80C186XL The 80C186XL is a very high integration 16-bit microprocessor It combines 15–20 of the most common microprocessor system components onto one chip The 80C186XL is object code compatible with the 8086 8088 microprocessors and adds 10 new instruction types to the 8086 8088 instruction set The 80C186XL has two major modes of operation Compatible and Enhanced In Compatible Mode the 80C186XL is completely compatible with NMOS 80186 with the exception of 8087 support The Enhanced mode adds three new features to the system design These are Power-Save control Dynamic RAM refresh and an asynchronous Numerics Coprocessor interface (80C186XL only) The 80C186XL oscillator circuit is designed to be used either with a parallel resonant fundamental or third-overtone mode crystal depending upon the frequency range of the application This is used as the time base for the 80C186XL The output of the oscillator is not directly available outside the 80C186XL The recommended crystal configuration is shown in Figure .


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