Document
80960KA EMBEDDED 32-BIT MICROPROCESSOR
s High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz s 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions s Multiple Register Sets — Sixteen Global 32-Bit Registers — Sixteen Local 32-Bit Registers — Four Local Register Sets Stored On-Chip — Register Scoreboarding s 4 Gigabyte, Linear Address Space s Pin Compatible with 80960KB The 80960KA is a member of Intel’s i960® 32-bit processor family, which is designed especially for embedded applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960KA has a large register set, multiple parallel execution units and a high-bandwidth burst bus. Using advanced RISC technology, this high performance processor is capable of execution rates in excess of 9.4 million instructions per second*. The 80960KA is well-suited for a wide range of applications including non-impact printers, I/O control and specialty instrumentation. s Built-in Interrupt Controller — 31 Priority Levels, 256 Vectors — 3.4 µs Latency @ 25 MHz s Easy to Use, High Bandwidth 32-Bit Bus — 66.7 Mbytes/s Burst — Up to 16 Bytes Transferred per Burst s 132-Lead Packages: — Pin Grid Array (PGA) — Plastic Quad Flat-Pack (PQFP)
SIXTEEN 32-BIT GLOBAL REGISTERS
64- BY 32-BIT LOCAL REGISTER CACHE
32-BIT INSTRUCTION EXECUTION UNIT
INSTRUCTION FETCH UNIT
512-BYTE INSTRUCTION CACHE
INSTRUCTION DECODER
MICROINSTRUCTION SEQUENCER
MICROINSTRUCTION ROM
32-BIT BUS CONTROL LOGIC
32-BIT BURST BUS
Figure 1. The 80960KA Processor’s Highly Parallel Architecture
* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment Corporation)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. May 1993 © INTEL CORPORATION, 1993 Order Number: 270775-005
80960KA EMBEDDED 32-BIT MICROPROCESSOR
1.0 THE i960® PROCESSOR ................................ 1 1.1. Key Performance Features .......................... 2 1.1.1. Memory Space And Addressing Modes . 4 1.1.2. Data Types ............................................. 4 1.1.3. Large Register Set ................................. 4 1.1.4. Multiple Register Sets ............................ 5 1.1.5. Instruction Cache ................................... 5 1.1.6. Register Scoreboarding ......................... 5 1.1.7. High Bandwidth Local Bus ..................... 6 1.1.8. Interrupt Handling ................................... 6 1.1.9. Debug Features ..................................... 6 1.1.10. Fault Detection ..................................... 7 1.1.11. Built-in Testability ................................. 7 1.1.12. CHMOS ................................................ 7 2.0 ELECTRICAL SPECIFICATIONS .................. 10 2.1. Power and Grounding ................................ 10 2.2. Power Decoupling Recommendations ....... 10 2.3. Connection Recommendations .................. 11 2.4. Characteristic Curves ................................. 11 2.5. Test Load Circuit ........................................ 14 2.6. Absolute Maximum Ratings ....................... 15 2.7. DC Characteristics ..................................... 15 2.8. AC Specifications ....................................... 16 2.8.1. AC Specification Tables ....................... 17 3.0 MECHANICAL DATA ..................................... 21 3.1. Packaging .................................................. 21 3.1.1. Pin Assignment .................................... 21 3.2. Pinout ......................................................... 25 3.3. Package Thermal Specification ................. 29 4.0. WAVEFORMS ............................................... 33 5.0. REVISION HISTORY ..................................... 38
FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. The 80960KA Processor’s Highly Parallel Architecture ............................ i 80960KA Programming Environment ........................................ 1 Instruction Formats ............................. 4 Multiple Register Sets Are Stored On-Chip ............................................... 6 Connection Recommendations for Low Current Drive Network .......... 11 Connection Recommendations for High Current Drive Network ......... 11 Typical Supply Current vs. Case Temperature ............................ 12 Typical Current vs. Frequency (Room Temp) .................................... 12 Typical Current vs. Frequency (Hot Temp) ......................................