80960JA

www.DataSheet4U.com A s s PRELIMINARY 80960JA/JF EMBEDDED 32-BIT MICROPROCESSOR Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers (8 sets) — Nine Addressing Modes — User/Supervisor Protection Model Two-Way Set Associative Instruction Cache — 80960JA - 2 Kbyte — 80960JF - 4 Kbyte — Programmable Cache Locking Mechanism Direct Mapped Data Cache — 80960JA - 1 Kbyte — 80960JF - 2 Kbyte — Write Through Operation On-Chip Stack Frame Cache — Seven Register Sets Can Be Saved — Automatic Allocation on Call/Return — 0-7 Frames Reserved for High-Priority Interrupts On-Chip Data RAM — 1 Kbyte Critical Variable Storage — Single-Cycle Access s High Bandwidth Burst Bus s s s s s s — 32-Bit Multiplexed Address/Data — Programmable Memory Configuration — Selectable 8-, 16-, 32-Bit Bus Widths — Supports Unaligned Accesses — Big or Little Endian Byte Ordering New Instructions — Conditional Add, Subtract and Select — Processor Management High-Speed Interrupt Controller — 31 Programmable Priorities — Eight Maskable Pins plus NMI — Up to 240 Vectors in Expanded Mode Two On-Chip Timers — Independent 32-Bit Counting — Clock Prescaling by 1, 2, 4 or 8 — lnternal Interrupt Sources Halt Mode for Low Power Compatibility s s IEEE 1149.1 (JTAG) Boundary Scan s Packages s — 132-Lead Pin Grid Array (PGA) — 132-Lead Plastic Quad F...