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80960JA Dataheets PDF



Part Number 80960JA
Manufacturers Intel Corporation
Logo Intel Corporation
Description EMBEDDED 32-BIT MICROPROCESSOR
Datasheet 80960JA Datasheet80960JA Datasheet (PDF)

www.DataSheet4U.com A s s PRELIMINARY 80960JA/JF EMBEDDED 32-BIT MICROPROCESSOR Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers (8 sets) — Nine Addressing Modes — User/Supervisor Protection Model Two-Way Set Associative Instruction Cache — 80960JA - 2 Kbyte — 80960JF - 4 Kbyte — Programmable Cache Locking Mechanism Direct Ma.

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www.DataSheet4U.com A s s PRELIMINARY 80960JA/JF EMBEDDED 32-BIT MICROPROCESSOR Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers (8 sets) — Nine Addressing Modes — User/Supervisor Protection Model Two-Way Set Associative Instruction Cache — 80960JA - 2 Kbyte — 80960JF - 4 Kbyte — Programmable Cache Locking Mechanism Direct Mapped Data Cache — 80960JA - 1 Kbyte — 80960JF - 2 Kbyte — Write Through Operation On-Chip Stack Frame Cache — Seven Register Sets Can Be Saved — Automatic Allocation on Call/Return — 0-7 Frames Reserved for High-Priority Interrupts On-Chip Data RAM — 1 Kbyte Critical Variable Storage — Single-Cycle Access s High Bandwidth Burst Bus s s s s s s — 32-Bit Multiplexed Address/Data — Programmable Memory Configuration — Selectable 8-, 16-, 32-Bit Bus Widths — Supports Unaligned Accesses — Big or Little Endian Byte Ordering New Instructions — Conditional Add, Subtract and Select — Processor Management High-Speed Interrupt Controller — 31 Programmable Priorities — Eight Maskable Pins plus NMI — Up to 240 Vectors in Expanded Mode Two On-Chip Timers — Independent 32-Bit Counting — Clock Prescaling by 1, 2, 4 or 8 — lnternal Interrupt Sources Halt Mode for Low Power Compatibility s s IEEE 1149.1 (JTAG) Boundary Scan s Packages s — 132-Lead Pin Grid Array (PGA) — 132-Lead Plastic Quad Flat Pack (PQFP) 132 PIN 1 99 A i A80960Jx XXXXXXXXA2 M © 19xx i960 ® i 33 NG80960Jx XXXXXXXXA2 M © 19xx 66 Figure 1. 80960JA/JF Microprocessors Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. © INTEL CORPORATION, 1995 September 1995 Order Number: 272504-004 www.DataSheet4U.com A 80960JA/JF EMBEDDED 32-BIT MICROPROCESSOR 80960JA/JF 1.0 PURPOSE ..................................................................................................................................................1 2.0 80960JA/JF OVERVIEW ............................................................................................................................1 2.1 80960 Processor Core ........................................................................................................................2 2.2 Burst Bus ............................................................................................................................................2 2.3 Timer Unit ...........................................................................................................................................3 2.4 Priority Interrupt Controller .................................................................................................................3 2.5 Instruction Set Summary ....................................................................................................................3 2.6 Faults and Debugging .........................................................................................................................3 2.7 Low Power Operation .........................................................................................................................4 2.8 Test Features ......................................................................................................................................4 2.9 Memory-Mapped Control Registers ....................................................................................................4 2.10 Data Types and Memory Addressing Modes ....................................................................................4 3.0 PACKAGE INFORMATION ........................................................................................................................6 3.1 Pin Descriptions .................................................................................................................................. 6 3.1.1 Functional Pin Definitions ........................................................................................................6 3.1.2 80960Jx 132-Lead PGA Pinout .............................................................................................13 3.1.3 80960Jx PQFP Pinout ...........................................................................................................17 3.2 Package Thermal Specifications ......................................................................................................20 4.0 ELECTRICAL SPECIFICATIONS ............................................................................................................22 4.1 Absolute Maximum Ratings ..............


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