Document
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR
Socket and Object Code Compatible with 80960CA Two Instructions Clock Sustained Execution Four 59 Mbytes s DMA Channels with Data Chaining Demultiplexed 32-bit Burst Bus with Pipelining
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32-bit Parallel Architecture Two Instructions clock Execution Load Store Architecture Sixteen 32-bit Global Registers Sixteen 32-bit Local Registers Manipulate 64-bit Bit Fields 11 Addressing Modes Full Parallel Fault Model Supervisor Protection Model Fast Procedure Call Return Model Full Procedure Call in 4 clocks On-Chip Register Cache Caches Registers on Call Ret Minimum of 6 Frames provided Up to 15 Programmable Frames On-Chip Instruction Cache 4 Kbyte Two-Way Set Associative 128-bit Path to Instruction Sequencer Cache-Lock Modes Cache-Off Mode On-Chip Data Cache 1 Kbyte Direct-Mapped Write Through 128 bits per Clock Access on Cache Hit Product Grades Available SE3 b 40 C to a 110 C
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High Bandwidth On-Chip Data RAM 1 Kbytes On-Chip RAM for Data Sustain 128 bits per clock access Four On-Chip DMA Channels 59 Mbytes s Fly-by Transfers 32 Mbytes s Two-Cycle Transfers Data Chaining Data Packing Unpacking Programmable Priority Method 32-Bit Demultiplexed Burst Bus 128-bit Internal Data Paths to and from Registers Burst Bus for DRAM Interfacing Address Pipelining Option Fully Programmable Wait States Supports 8 16 or 32-bit Bus Widths Supports Unaligned Accesses Supervisor Protection Pin Selectable Big or Little Endian Byte Ordering High-Speed Interrupt Controller Up to 248 External Interrupts 32 Fully Programmable Priorities Multi-mode 8-bit Interrupt Port Four Internal DMA Interrupts Separate Non-maskable Interrupt Pin Context Switch in 750 ns Typical
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COPYRIGHT
INTEL CORPORATION 1995
January 1995
Order Number 271328-001
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
271328 – 1
Figure 1 80960CF Die Photo
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Special Environment 80960CF-30 -25 -16 32-Bit High Performance Superscalar Processor
CONTENTS
1 0 PURPOSE 2 0 i960 CF PROCESSOR OVERVIEW 2 1 The C-Series Core 2 2 Pipelined Burst Bus 2 3 Flexible DMA Controller 2 4 Priority Interrupt Controller 2 5 Instruction Set Summary 3 0 PACKAGE INFORMATION 3 1 Package Introduction 3 2 Pin Descriptions 3 3 80960CF Pinout 3 4 Mechanical Data 3 5 Package Thermal Specifications 3 6 Stepping Register Information 3 7 Suggested Source.