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SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
Two Instructions Clock Sustained Execution Four 59 Mbytes s DMA Channels with Data Chaining Demultiplexed 32-bit Burst Bus with Pipelining
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32-bit Parallel Architecture Two Instructions clock Execution Load Store Architecture Sixteen 32-bit Global Registers Sixteen 32-bit Local Registers Manipulates 64-bit Bit Fields 11 Addressing Modes Full Parallel Fault Model Supervisor Protection Model Fast Procedure Call Return Model Full Procedure Call in 4 Clocks On-Chip Register Cache Caches Registers on Call Ret Minimum of 6 Frames Provided Up to 15 Programmable Frames On-Chip instruction Cache 1 Kbyte Two-Way Set Associative 128-bit Path to instruction Sequencer Cache-Lock Modes Cache-Off Mode High Bandwidth On-Chip Data RAM 1 Kbyte On-Chip Data RAM Sustains 128 bits per Clock Access
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Four On-Chip DMA Channels 59 Mbytes s Fly-by Transfers 32 Mbytes s Two-Cycle Transfers Data Chaining Data Packing Unpacking Programmable Priority Method 32-Bit Demultiplexed Burst Bus 128-bit internal Data Paths to and from Registers Burst Bus for DRAM Interfacing Address Pipelining Option Fully Programmable Wait States Supports 8- 16- or 32-bit Bus Widths Supports Unaligned Accesses Supervisor Protection Pin Selectable Big or Little Endian Byte Ordering High-Speed Interrupt Controller Up to 248 External interrupts 32 Fully Programmable Priorities Multi-mode 8-bit Interrupt Port Four internal DMA Interrupts Separate Non-maskable interrupt Pin Context Switch in 750 ns Typical Product Grades Available SE3 b 40 C to a 110 C
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December 1994
Order Number 271327-001
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SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
CONTENTS
1 0 PURPOSE 2 0 80960CA OVERVIEW 2 1 The C-Series Core 2 2 Pipelined Burst Bus 2 3 Flexible DMA Controller 2 4 Priority Interrupt Controller 2 5 Instruction Set Summary 3 0 PACKAGE INFORMATION 3 1 Package Introduction 3 2 Pin Descriptions 3 3 80960CA Mechanical Data 3 3 1 80960CA PGA Pinout 3 4 Package Thermal Specifications 3 5 Stepping Register Information 3 6 Suggested Sources for 80960CA Accessories 4 0 ELECTRICAL SPECIFICATIONS 4 1 Absolute Maximum Ratings 4 2 Operating Conditions 4 3 Recommended Connections 4 4 DC Specifications 4 5 AC Specifications 4 5 1 AC Test Conditions 4 5 2 AC Timing Waveforms 4 5 3 Derating Curves 5 0 RESET BACKOFF AND HOLD ACKNOWLEDGE 6 0 BUS WAVEFORMS 7 0 REVISION HISTORY PAGE
5 5 6 6 6 6 7 8 8 8 15 15 19 21 21 22 22 22 22 23 24 28 28 32 34 35 62
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CONTENTS
LIST OF FIGURES Figure 1 80960CA Block Diagram Figure 2 80960CA PGA Pinout View from Top (Pins Facing Down) Figure 3 80960CA PGA Pinout View from Bottom (Pins Facing Up) Figure 4 Measuring 80960CA PGA Case Temperature Figure 5 Register g0 Figure 6 AC Test Load Figure 7 Input and Output Clocks Waveform Figure 8 CLKIN Waveform Figure 9 Output Delay and Float Waveform Figur.