M88K

M88 FAMILY In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems (with CPLD) for MCUs DATA BRIEFING s s Single Supply Voltage: – 5 V±10% for M88xxFxY – 3 V (+20/–10%) for M88xxFxW 1 or 2 Mbit of Primary Flash Memory (8 uniform sectors, 16K x 8, or 32K x 8) A second non-volatile memory: – 256 Kbit (32K x 8) EEPROM (for M8813F1x) or Flash memory (for M88x3F2x) – 4 uniform sectors (8K x 8) SRAM (16 Kbit, 2K x 8; or 64 Kbit, 8K x 8) Over 3,000 Gates of PLD: DPLD and CPLD 27 Reconfigurable I/O ports Enhanced JTAG Serial Port Programmable power management Stand-by current: – 50 µA for M88xxFxY – 25 µA for M88xxFxW High Endurance: – 100,000 Erase/Write Cycles of Flash Memory – 10,000 Erase/Write Cycles of EEPROM – 1,000 Erase/Write Cycles of PLD PQFP52 (T) s s s s s s s s PLCC52 (K) Figure 1. Logic Diagram VCC DESCRIPTION The FLASH+PSD family of memory systems for microcontrollers (MCUs) brings In-SystemTable 1. Signal Names PA0-PA7 PB0-PB7 PC0-PC7 PC2 = Voltage Stand-by PD0-PD2 AD0-AD15 CNTL0-CNTL2 RESET VCC VSS Port-D Address/Data Control Reset Supply Voltage Ground Port-A Port-B Port-C 8 PA0-PA7 3 CNTL0CNTL2 16 AD0-AD15 3 RESET PD0-PD2 FLASH+PSD 8 PC0-PC7 8 PB0-PB7 VSS AI02856 June 2000 Complete data available on Data-on-Disc CD-ROM or at www.st.com 1/7 M88 FAMILY Figure 2A. PLCC Connections CNTL1 CNTL2 RESET CNTL0 PB0 PB1 PB2 PB3 PB4 PB5 GND PB6 PB7 Figure 2B. PQFP Connections 40 CNTLO PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 PC1 PC0 8 9 10...