M74HC75

M54HC75 M74HC75 4 BIT D TYPE LATCH . . . . . . . . HIGH SPEED tPD = 10 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC = (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS75 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC75F1R M74HC75M1R M74HC75B1R M74HC75C1R DESCRIPTION The M54/74HC75 is a high speed CMOS 4-BIT DTYPE LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. It contains two groups of 2-bit latches controlled by an enable input (G12 or G34). These two latch groups can be used in different circuits. Each latch has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The data applied to the data input is transfered to the Q and Q outputs when the enable input is taken high and the outputs will follow the data input as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input is retained at the outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection December 1992 1...