DatasheetsPDF.com

M6MGB160S2BVP Dataheets PDF



Part Number M6MGB160S2BVP
Manufacturers Mitsubishi
Logo Mitsubishi
Description CMOS 3.3V-ONLY FLASH MEMORY & CMOS SRAM Stacked-MCP
Datasheet M6MGB160S2BVP DatasheetM6MGB160S2BVP Datasheet (PDF)

M6MGB/T160S2BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) MITSUBISHI LSIs DESCRIPTION FEATURES The MITSUBISHI M6MGB/T160S2BVP is a Stacked Multi • Access time Chip Package (S-MCP) that contents 16M-bits flash memory Flash Memory 90ns (Max.) and 2M-bits Static RAM in a 48-pin TSOP (TYPE-I). SRAM 85ns (Max.) • Supply voltage Vcc=2.7 ~ .

  M6MGB160S2BVP   M6MGB160S2BVP


Document
M6MGB/T160S2BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) MITSUBISHI LSIs DESCRIPTION FEATURES The MITSUBISHI M6MGB/T160S2BVP is a Stacked Multi • Access time Chip Package (S-MCP) that contents 16M-bits flash memory Flash Memory 90ns (Max.) and 2M-bits Static RAM in a 48-pin TSOP (TYPE-I). SRAM 85ns (Max.) • Supply voltage Vcc=2.7 ~ 3.6V 16M-bits Flash memory is a 2097152 bytes /1048576 words, • Ambient temperature 3.3V-only, and high performance non-volatile memory W version Ta=-20 ~ 85°C fabricated by CMOS technology for the peripheral circuit • Package : 48-pin TSOP (Type-I) , 0.4mm lead pitch and DINOR(DIvided bit-line NOR) architecture for the memory cell. 2M-bits SRAM is a 262144 bytes / 131072 words APPLICATION unsynchronous SRAM fabricated by silicon-gate CMOS technology. Mobile communication products M6MGB/T160S2BVP is suitable for the application of the mobile-communication-system to reduce both the mount space and weight . PIN CONFIGURATION (TOP VIEW) A15 A14 A13 A12 A11 A10 A9 A8 A19 S-CE WE# F-RP# F-WP# S-VCC F-RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 F-VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND F-CE# A0 10.0 mm 14.0 mm F-VCC S-VCC GND A-1-A16 A17-A19 DQ0-DQ15 F-CE# S-CE OE# WE# F-WP# F-RP# F-RY/BY# BYTE# :Vcc for Flash NC:Non Connection :Vcc for SRAM :GND for Flash/SRAM :Flash/SRAM common Address :Address for Flash :Data I/O :Flash Chip Enable :SRAM Chip Enable :Flash/SRAM Output Enable :Flash/SRAM Write Enable :Flash Write Protect :Flash Reset Power Down :Flash Ready /Busy :Flash/SRAM Byte Enable 1 Sep. 1999 , Rev.2.0 M6MGB/T160S2BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) MITSUBISHI LSIs BLOCK DIAGRAM 16Mb Flash Memory A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128 WORD PAGE BUFFER Main Block 32KW F-VCC(3.3V) 28 Bank(II) GND (0V) Main Block Parameter Block7 Parameter Block6 Parameter Block5 Parameter Block4 Parameter Block3 Parameter Block2 Parameter Block1 Boot Block X-DECODER Bank(I) 32KW 16KW 16KW 16KW 16KW 16KW 16KW 16KW 16KW ADDRESS INPUTS Y-DECODER Y-GATE / SENSE AMP. STATUS / ID REGISTER MULTIPLEXER CHIP ENABLE INPUT OUTPUT ENABLE INPUT WRITE ENABLE INPUT WRITE PROTECT INPUT RESET/POWER DOWN INPUT BYTE ENABLE INPUT READY/BUSY OUTPUT F-CE# OE# WE# F-WP# F-RP# BYTE# CUI WSM INPUT/OUTPUT BUFFERS F-RY/BY# DQ15/A-1 DQ14DQ13 DQ12 DQ3DQ2 DQ1DQ0 2Mb SRAM ADDRESS INPUT BUFFER SENSE AMP. A-1 A0 DATA INPUTS/OUTPUTS ROW DECODER SENSE AMP. 262144 WORD x 8 BITS or 131072 WORD x 16 BITS OUTPUT BUFFER DQ 0 DQ 7 A15 A16 OUTPUT BUFFER DQ 8 DQ15/A-1 S-CE DATAINPUT BUFFER CLOCK GENERATOR S-VCC DATAINPUT BUFFER BYTE# WE# OE# GND 2 Sep. 1999 , Rev.2.0 M6MGB/T160S2BVP 16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) MITSUBISHI LSIs 1. Flash Memory DESCRIPTION The Flash Memory of M6MGB/T160S2BVP is 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for mobile and personal computing, and communication products. The Flash Memory of M6MGB/T160S2BVP is fabricated by CMOS technology for the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells. FEATURES Organization .................................1048,576 word x 16bit .................................2,097,152 word x 8 bit Boot Block M6MGB160S2BVP ........................ Bottom Boot M6MGT160S2BVP ........................ Top Boot Other Functions Soft Ware Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Alternating Back Ground Program/Erase Operation Between Bank(I) and Bank(II) ............................. VCC = 2.7~3.6V Supply voltage ................................ Access time .............................. 90ns (Max.) Power Dissipation ................................. 54 mW (Max. at 5MHz) Read (After Automatic Power saving) .......... 0.33mW (typ.) Program/Erase .................................126 mW (Max.) ................................. 0.33mW (typ.) Standby Deep power down mode ....................... 0.33mW (typ.) Auto program for Bank(I) ..........


M6MFT16S2TP M6MGB160S2BVP M6MGB160S4BVP


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)