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74VHC574 Dataheets PDF



Part Number 74VHC574
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description Octal D-Type Flip-Flop
Datasheet 74VHC574 Datasheet74VHC574 Datasheet (PDF)

® 74VHC574 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING s s s s s s s s s s HIGH SPEED: fMAX = 180 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY L.

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® 74VHC574 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING s s s s s s s s s s HIGH SPEED: fMAX = 180 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY LOW NOISE VOLP = 0.9V (Max.) M (Micro Package) T (TSSOP Package) ORDER CODES : 74VHC574M 74VHC574T at the D inputs. While the OE input is low, the 8 outputs will be in a normal logic state (high or low logic level) and, while high level, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip flop; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. DESCRIPTION The 74VHC574 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. This 8 bit D-Type flip-flop is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to logic states that were setup PIN CONNECTION AND IEC LOGIC SYMBOLS June 1999 1/10 74VHC574 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 SYMBOL OE D0 to D7 NAME AND FUNCT ION 3 State Output Enable Input (Active LOW) Data Inputs Q0 to Q7 3 State Outputs CLOCK GND VCC Clock Input (LOW to HIGH, edge triggered) Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OE H L L L X:Don’t Care Z: High Impedance OUT PUTS D X X L H Q Z NO CHANGE L H CK X LOGIC DIAGRAM 2/10 74VHC574 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 75 -65 to +150 300 Unit V V V mA mA mA mA o o ICC or IGND DC VCC or Ground Current C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (see note 1) (VCC = 3.3 ± 0.3V) (V CC = 5.0 ± 0.5V) Parameter Valu e 2.0 to 5.5 0 to 5.5 0 to VCC -40 to +85 0 t.


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