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74VHC4066 Dataheets PDF



Part Number 74VHC4066
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Quad Analog Switch/Multiplexer/Demultiplexer
Datasheet 74VHC4066 Datasheet74VHC4066 Datasheet (PDF)

74VHC4066 Quad Analog Switch April 1994 Revised January 2000 74VHC4066 Quad Analog Switch General Description These devices are digitally controlled analog switches utilizing advanced silicon-gate CMOS technology. These switches have low “on” resistance and low “off” leakages. They are bidirectional switches, thus any analog input may be used as an output and visa-versa. Also the 4066 switches contain linearization circuitry which lowers the “on” resistance and increases switch linearity. The .

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74VHC4066 Quad Analog Switch April 1994 Revised January 2000 74VHC4066 Quad Analog Switch General Description These devices are digitally controlled analog switches utilizing advanced silicon-gate CMOS technology. These switches have low “on” resistance and low “off” leakages. They are bidirectional switches, thus any analog input may be used as an output and visa-versa. Also the 4066 switches contain linearization circuitry which lowers the “on” resistance and increases switch linearity. The 4066 devices allow control of up to 12V (peak) analog signals with digital control signals of the same range. Each switch has its own control input which disables each switch when low. All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to VCC and ground. Features s Typical switch enable time: 15 ns s Wide analog input voltage range: 0–12V s Low “on” resistance: 30 typ. ('4066) s Low quiescent current: 80 µA maximum (74VHC) s Matched switch characteristics s Individual switch controls s Pin and function compatible with the 74HC4066 Ordering Code: Order Number 74VHC4066M 74VHC4066MTC 74VHC4066N Package Number M14A MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Schematic Diagram Top View Truth Table Input CTL L H Switch I/O–O/I “OFF” “ON” © 2000 Fairchild Semiconductor Corporation DS011677 www.fairchildsemi.com 74VHC4066 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Control Input Voltage (VIN) DC Switch I/O Voltage (VIO) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C −0.5 to +15V −1.5 to VCC + 1.5V VEE − 0.5 to VCC + 0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times VCC = 2.0V VCC = 4.5V VCC = 9.0V (tr, tf) 1000 500 400 ns ns ns −40 +85 °C 2 0 Max 12 VCC Units V V Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage (Note 4) Conditions VCC 2.0V 4.5V 9.0V 12.0V TA=25°C Typ 1.5 3.15 6.3 8.4 0.5 1.35 2.7 3.6 100 50 30 120 50 35 20 10 5 5 170 85 70 180 80 60 40 15 10 10 ±0.05 6.0V 9.0V 12.0V 6.0V 9.0V 12.0V 6.0V 9.0V 12.0V 10 15 20 10 15 20 ±60 ±80 ±100 ±40 ±50 ±60 1.0 2.0 4.0 TA=−40 to 85°C Guaranteed Limits 1.5 3.15 5.3 8.4 0.5 1.35 2.7 3.6 200 105 85 215 100 75 60 20 15 15 ±0.5 ±600 ±800 ±1000 ±150 ±200 ±300 10 20 40 Units V V V V V V V V Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω µA nA nA nA nA nA nA µA µA µA VIL Maximum LOW Level Input Voltage 2.0V 4.5V 9.0V 12.0V RON Maximum “ON” Resistance See (Note 5) VCTL = VIH, IS = 2.0 mA VIS = V CC to GND (Figure 1) VCTL = VIH, IS = 2.0 mA VIS = V CC or GND (Figure 1) 4.5V 9.0V 12.0V 2.0V 4.5V 9.0V 12.0V 4.5V 9.0V 12.0V RON Maximum “ON” Resistance Matching VCTL = VIH VIS = V CC to GND VIN = VCC or GND VCC = 2 − 6V VOS = V CC or GND VIS = GND or VCC VCTL = VIL (Figure 2) VIS = V CC to GND VCTL = VIH VOS = OPEN (Figure 3) VIN = VCC or GND IOUT = 0 µA IIN IIZ Maximum Control Input Current Maximum Switch “OFF” Leakage Current IIZ Maximum Switch “ON” Leakage Current ICC Maximum Quiescent Supply Current Note 4: For a power supply of 5V ± 10% the worst case on resistance (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs for CMOS at the higher voltage and so the 5.5V values should be used. Note 5: At supply voltages (VCC – GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital only when using these supply voltages. www.fairchildsemi.com 2 74VHC4066 AC Electrical Characteristics VCC = 2.0V−6.0V VEE = 0V−12V, CL = 50 pF (unless otherwise specified) Symbol tPHL, tPLH Parameter Maximum Propagation Delay Switch In to Out Conditions VCC 3.3V 4.5V 9.0V 12.0V tPZL, tPZH Maximum Switch Turn “ON” Delay RL = 1 kΩ 3.3V 4.5V 9.0V 12.0V tPHZ, tPLZ Maximum Switch Turn “OFF” Delay RL = 1 kΩ 3.3V 4.5V 9.0V 12.0V Minimum Frequency Response (Figure 7) 20 log(VO.


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