SDA9188-3X

Picture-in-Picture Processor with On-Chip PLL SDA 9188-3X Preliminary Data MOS IC Features q On-chip PLL q Full frame display for 50/60 Hz in order to increase the vertical resolution and to suppress moving artifacts. q Compatibility to the 16:9 display format by means of q q q q q q independent setting of the vertical and horizontal decimation factors and the width of the border frame Decimation of the Y, U, V data for pictures sizes 1/9 and 1/16 with 6 bits width of the input word without P-DSO-28-3 rounding error Intermediate storage of the inset picture (on-chip-memory) RGB- or Y-, U-, V-signal generation 100% pin- and software compatible with SDA 9188X if external PLL is used Increased bandwith of analog outputs due to higher output currents New select function for multi-PIP feature Type SDA 9188-3X Functional Description Ordering Code Q67100-H5142 Package P-DSO-28-3 (350 mil) (SMD) The SDA 9188-3X Picture-in-Picture (PIP) processor with on-chip PLL combines two asynchronous picture sources so that a small moving picture (the inset picture) can be superimposed in a moving picture of normal size (the parent picture). The components of the video signal of the inset source have to be fed in a digitized form to the SDA 9188-3X (figure 1). Amplitude resolution of the signal components is 6 bit at a sampling rate of 13.5 MHz for the luminance signal and 3.375 MHz for the chrominance signals. Semiconductor Group 1 08.93 SDA 9188-3X The PIP processor SDA 9188-3X...