SDA5648

Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder SDA 5648 SDA 5648X CMOS IC Features q Single-chip receiver for PDC data, broadcast either q q q q q q q q q q q – in Broadcast Data Service Packet (BDSP) 8/30/2 according to CCIR teletext system B, or – in dedicated line no. 16 of the vertical blanking interval (VPS) Reception of Unified Date and Time (UDT) broadcast in BDSP 8/30/1 Low external components count On-chip data and sync slicer I2C-Bus interface for communication with external microcontroller Selection of PDC/VPS operating mode software controlled by I2C-Bus register Pin and software compatible to VPS Decoder SDA 5642 Supply voltage: 5 V ± 10 % Video input signal level: 0.7 Vpp to 1.4 Vpp Technology: CMOS Package: P-DIP-14-3 and P-DSO-20-1 Operating temperature range: 0 to 70 °C P-DIP-14-3 P-DSO-20-1 Type SDA 5648 SDA 5648X Functional Description Ordering Code Q67000-A5186 Q67006-A5198 Package P-DIP-14-3 P-DSO-20-1 Tape & Reel The CMOS circuit SDA 5648 is intended for use in video cassette recorders to retrieve control data of the PDC system from the data lines broadcast during the vertical blanking interval of a standard video signal. The SDA 5648 is devised to handle PDC data transported either in Broadcast Data Service Packet (BDSP) 8/30 format 2 (bytes no. 13 through 25) of CCIR teletext system B or in the dedicated data line no. 16 in the case of VPS. Furthermore it is able to receive the Unified Date and Time (UDT) inf...