MCM72JG32

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order Order this this document document by by MCM72JG32/D MCM72JG32/D Advance Information 256K and 512K Pipelined BurstRAM™ Sedcondary Cache Module for Pentium™ The MCM72JG32 and MCM72JG64 are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton chip set. The modules are configured as 32K x 64 and 64K x 64 bits in a 160 pin card edge memory module. Each module uses four of Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and one Motorola 5 V 32K x 8 FSRAM for the tag RAM. Bursts can be initiated with either address status processor (ADSP) or cache address status (CADS). Subsequent burst addresses are generated internal to the BurstRAM by the cache burst advance (CADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLK0, CLK1) input. Eight write enables are provided for byte write control. PD0 – PD4 map into the Triton chip set for auto–configuration of the cache control. Module family pinout supports 5 V and 3.3 V components. It is recommended that all power supplies be connected. These cache modules are plug and pin compatible with the MCM64AF32SG15, a 256K byte asynchronous module also designed for the Pentium microprocessor in conjunction with Intel’s Triton chip set. Pentium–Style Burst Counter on Chip Pipelined Data Out 160 Pin Card Edge Module Address Pipeline Supported by ADSP Disabled wi...