OCTAL BUS BUFFER
74VHC240
OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)
s HIGH SPEED: tPD = 3.6ns (TYP.) at VCC = 5V
s LOW POWER DIS...
Description
74VHC240
OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)
s HIGH SPEED: tPD = 3.6ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
SOP
TSSOP
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
)s OPERATING VOLTAGE RANGE: t(sVCC(OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
uc74 SERIES 240 ds IMPROVED LATCH-UP IMMUNITY ros LOW NOISE: VOLP = 0.9V (MAX.) PDESCRIPTION teThe 74VHC240 is an advanced high-speed leCMOS OCTAL BUS BUFFER (3-STATE) ofabricated with sub-micron silicon gate and sdouble-layer metal wiring C2MOS technology. bG output enable governs four BUS BUFFERs. OThis device is designed to be used with 3 state -memory address drivers, etc.
Table 1: Order Codes
PACKAGE SOP
TSSOP
T&R
74VHC240MTR 74VHC240TTR
Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
Obsolete Product(s)Figure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 5
1/12
74VHC240
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
PIN N°
1 2, 4, 6, 8 9, 7, 5, 3 11, 13, 15,
17 18, 16, 14,
12 19 10 20
SYMBOL NAME AND FUNCTION
1G 1A1 to 1A4 2...
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