MCM67H618B

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67H618B/D Advance Information MCM67H618B 64K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self–Timed Write The MCM67H618B is a 1,179,648 bit synchronous fast static random access memory designed to provide a burstable, high–performance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 – A15), data inputs (D0 – D17), and all control signals DQ9 except output enable (G) are clock (K) controlled through positive– DQ10 edge–triggered noninverting registers. VCC Bursts can be initiated with either address status processor (ADSP) VSS or address status cache controller (ADSC) input pins. Subsequent DQ11 burst addresses can be generated internally by the MCM67H618B DQ12 (burst sequence imitates that of the i486 and Pentium) and controlled DQ13 by the burst address advance (ADV) input pin. The following pages proDQ14 vide more detailed information on bu...