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MCM63Z736 Dataheets PDF



Part Number MCM63Z736
Manufacturers Motorola
Logo Motorola
Description 128K x 36 and 256K x 18 Bit Pipelined ZBT RAM Synchronous Fast Static RAM
Datasheet MCM63Z736 DatasheetMCM63Z736 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63Z736/D Advance Information 128K x 36 and 256K x 18 Bit Pipelined ZBT™ RAM Synchronous Fast Static RAM The ZBT RAM is a 4M–bit synchronous fast static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during back–to–back read/write and write/read cycles. The MCM63Z736 is organized as 128K words of 36 bits each and the MCM63Z818 is organized as 256K words of 18 bits each, fabricated with high.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63Z736/D Advance Information 128K x 36 and 256K x 18 Bit Pipelined ZBT™ RAM Synchronous Fast Static RAM The ZBT RAM is a 4M–bit synchronous fast static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during back–to–back read/write and write/read cycles. The MCM63Z736 is organized as 128K words of 36 bits each and the MCM63Z818 is organized as 256K words of 18 bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQ), and all control signals except output enable (G) and linear burst order (LBO) are clock (CK) controlled through positive– edge–triggered noninverting registers. Write cycles are internally self–timed and are initiated by the rising edge of the clock (CK) input. This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge– triggered output register and then released to the output buffers at the next rising edge of clock (CK). • 3.3 V LVTTL and LVCMOS Compatible • MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz) MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz) • Selectable Burst Sequencing Order (Linear/Interleaved) • Internally Self–Timed Write Cycle • Two–Cycle Deselect • Byte Write Control • ADV Controlled Burst • 100–Pin TQFP Package MCM63Z736 MCM63Z818 TQ PACKAGE TQFP CASE 983A–01 ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc. and Motorola, Inc. This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 1 2/6/98 © Motorola, Inc. 1998 MOTOROLA FAST SRAM MCM63Z736DMCM63Z818 1 PIN ASSIGNMENT SA SA SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS CK SW CKE G ADV NC NC SA SA DQc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VDD VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQd 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50 LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA DQb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS VDD VDD VSS DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQa TOP VIEW MCM63Z736 MCM63Z736DMCM63Z818 2 MOTOROLA FAST SRAM PIN ASSIGNMENT SA SA SE1 SE2 NC NC SBb SBa SE3 VDD VSS CK SW CKE G ADV NC NC SA SA NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VDD VDD VDD VSS DQb DQb VDDQ VSS DQb DQb DQb NC VSS VDDQ NC NC NC 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50 LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA SA NC NC VDDQ VSS NC DQa DQa DQa VSS VDDQ DQa DQa VSS VDD VDD VSS DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC TOP VIEW MCM63Z818 MOTOROLA FAST SRAM MCM63Z736DMCM63Z818 3 MCM63Z736 PIN DESCRIPTIONS Pin Locations 85 89 87 (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 86 31 Symbol ADV CK CKE DQx Type Input Input Input I/O Description Synchronous Load/Advance: Loads a new address into counter when low. RAM uses internally generated burst addresses when high. Clock: This signal registers the address, data in, and all control signals except G and LBO. Clock Enable: Disables the CK input when CKE is high. Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b, c, d). G LBO Input Input Asynchronous Output Enable. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low – linear burst counter. High – interleaved burst counter. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Burst Address Inputs: The two LSB’s of the address field. These pins must preset the burst address counter values. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: Enables write to byte “x” (byte a,.


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