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MCM6227A Dataheets PDF



Part Number MCM6227A
Manufacturers Motorola
Logo Motorola
Description 1M x 1 Bit Static Random Access Memory
Datasheet MCM6227A DatasheetMCM6227A Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6227A/D 1M x 1 Bit Static Random Access Memory The MCM6227A is a 1,048,576 bit static random–access memory organized as 1,048,576 words of 1 bit, fabricated using high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6227A is equipped with a chip enable (E) pin. In less than .

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6227A/D 1M x 1 Bit Static Random Access Memory The MCM6227A is a 1,048,576 bit static random–access memory organized as 1,048,576 words of 1 bit, fabricated using high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6227A is equipped with a chip enable (E) pin. In less than a cycle time after E goes high, the part enters a low–power standby mode, remaining in that state until E goes low again. The MCM6227A is available in 400 mil, 28–lead surface–mount SOJ packages. • • • • • • Single 5 V ± 10% Power Supply Fast Access Times: 20, 25, 35, and 45 ns Equal Address and Chip Enable Access Times Input and Output are TTL Compatible Three–State Output Low Power Operation: 160/140/130/120 mA Maximum, Active AC MCM6227A WJ PACKAGE 400 MIL SOJ CASE 810–03 PIN ASSIGNMENT A0 A1 A2 A3 A4 A5 NC A6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A19 A18 A17 A16 A15 A14 NC A13 A12 A11 A10 D E BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER MEMORY MATRIX 1024 ROWS x 1024 COLUMNS V CC VSS A7 A8 A9 Q W VSS PIN NAMES A0 – A19 . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . Write Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable D . . . . . . . . . . . . . . . . . . . . . . . . Data Input Q . . . . . . . . . . . . . . . . . . . . . Data Output NC . . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . Ground D INPUT DATA CONTROL COLUMN I/O COLUMN DECODER Q E A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 W REV 4 5/95 © Motorola, Inc. 1994 MOTOROLA FAST SRAM MCM6227A 1 MCM6227A TRUTH TABLE E H L L W X H L Mode Not Selected Read Write I/O Pin High–Z Dout High–Z Cycle — Read Write Current ISB1, ISB2 ICCA ICCA H = High, L = Low, X = Don’t Care ABSOLUTE MAXIMUM RATINGS (See Note) Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value – 0.5 to 7.0 – 0.5 to VCC + 0.5 ± 20 1.1 – 10 to + 85 0 to + 70 Unit V V mA W °C °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. Storage Temperature Tstg .


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