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MCM6209C Dataheets PDF



Part Number MCM6209C
Manufacturers Motorola
Logo Motorola
Description 64K x 4 Bit Fast Static RAM
Datasheet MCM6209C DatasheetMCM6209C Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6209C/D 64K x 4 Bit Fast Static RAM With Output Enable The MCM6209C is fabricated using Motorola’s high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in plastic dual–in–line and plastic small–outlin.

  MCM6209C   MCM6209C



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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6209C/D 64K x 4 Bit Fast Static RAM With Output Enable The MCM6209C is fabricated using Motorola’s high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in plastic dual–in–line and plastic small–outline J–leaded packages. Single 5 V ± 10% Power Supply Fully Static — No Clock or Timing Strobes Necessary Fast Access Times: 12, 15, 20, 25, and 35 ns Equal Address and Chip Enable Access Times Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems • Low Power Operation: 135 – 165 mA Maximum AC • Fully TTL Compatible — Three–State Output • • • • • MCM6209C P PACKAGE 300 MIL PLASTIC CASE 710B–01 J PACKAGE 300 MIL SOJ CASE 810B–03 PIN ASSIGNMENT NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A15 A14 A13 A12 A11 A10 NC NC DQ0 DQ1 DQ2 DQ3 W BLOCK DIAGRAM A1 A2 A3 A4 A6 A12 A13 A14 ROW DECODER MEMORY ARRAY 256 ROWS x 64 x 4 COLUMNS VCC VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 E G DQ0 DQ1 DQ2 DQ3 INPUT DATA CONTROL COLUMN I/O COLUMN DECODER VSS PIN NAMES A0 A5 A7 A8 A9 A10 A11 A15 A0 – A15 . . . . . . . . . . . . . Address Input DQ0 – DQ3 . . . Data Input/Data Output W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable NC . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . Power Supply (+ 5 V) VSS . . . . . . . . . . . . . . . . . . . . . . . Ground E W G REV 3 5/95 © Motorola, Inc. 1995 MOTOROLA FAST SRAM MCM6209C 1 TRUTH TABLE (X = Don’t Care) E H L L L G X H L X W X H H L Mode Not Selected Output Disabled Read Write VCC Current ISB1, ISB2 ICCA ICCA ICCA Output High–Z High–Z Dout High–Z Cycle — — Read Write ABSOLUTE MAXIMUM RATINGS (See Note) Rating Power Supply Voltage Voltage Relative to VSS For Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature — Plastic Symbol VCC Vin, Vout Iout PD Tbias TA Value – 0.5 to + 7.0 – 0.5 to VCC + 0.5 ± 20 1.0 – 10 to + 85 0 to + 70 Unit V V mA W °C °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 – 0.5* Typ 5.0 — — Max 5.5 VCC + 0.3** 0.8 Unit V V V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC) Standby Current (E ≥ VCC – 0.2 V*, Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V, VCC = Max, f = 0 MHz) Output Low Voltage (IOL = 8.0 mA) Output High Voltage (IOH = – 4.0 mA) Symbol Ilkg(I) Ilkg(O) ISB2 VOL Min — — — — Max ±1 ±1 20 0.4 — Unit µA µA mA V V VOH 2.4 *For devices with multiple chip enables, E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E. POWER SUPPLY CURRENTS Parameter AC Supply Current (Iout = 0 mA, VCC = Max, f = fmax) Standby Current (E = VIH , VCC = Max, f = fmax) Symbol ICCA ISB1 – 12 165 55 – 15 155 50 – 20 145 45 – 25 135 40 – 35 130 35 Unit mA mA MCM6209C 2 MOTOROLA FAST SRAM CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Characteristic Address Input Capacitance Control Pin Input Capacitance (E, G, W) I/O Capacitance Symbol Cin Cin CI/O Max 6 6 8 Unit pF pF pF AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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