MC88914N

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document from Logic Marketing Low Skew CMOS Clock Driver With Reset The MC88914 is a high–speed, low power, hex divide–by–two D–type flip–flop with matched propagation delays, an internal power–on–reset, and external synchronous reset. With TTL compatible buffered clock and external reset inputs that are common to all flip–flops, the MC88914 is ideal for use in high–frequency systems as a clock driver, providing multiple outputs that are synchronous. MC88914 LOW SKEW CMOS CLOCK DRIVER WITH RESET Power–on–Reset and External Synchronous Reset TTL Compatible Positive Edge–Triggered Clock Matched Outputs for Synchronous Applications Outputs Source/Sink 24mA Part–to–Part Skew of Less Than 3.0ns Guaranteed Rise and Fall Times for a Given Capacitive Load 14 1 Pinout: 14–Lead Plastic (Top View) VCC 14 GND 13 Q5 12 Q4 11 Q3 10 SR 9 GND 8 N SUFFIX PLASTIC PACKAGE CASE 646–06 14 1 1 VCC 2 GND 3 Q0 4 Q1 5 Q2 6 CLK 7 GND D SUFFIX PLASTIC PACKAGE CASE 751A–03 LOGIC DIAGRAM SR POWER–ON RESET CLK CLK D RST Q CLK D RST Q CLK D RST Q CLK D RST Q CLK D RST Q CLK D RST Q Q0 Q1 Q2 Q3 Q4 Q5 NOTE: This diagram is provided only for understanding of logic operation and should not be used to estimate propagation delays 8/95 © Motorola, Inc. 1995 1 REV 4 MC88914 DC CHARACTERISTICS (unless otherwise specified) Symbol ICC Parameter Maximum Quiescent Supply Current 80 Unit µA Condition VIN = VCC or GND VCC = 5...