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74VCX32374 Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
December 2000 Revised November 2002
74VCX32374 Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32374 contains thirty-two non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 32-bit operation. The 74VCX32374 is designed for low voltage (1.2V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74VCX32374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.2V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD 3.0 ns max for 3.0V to 3.6V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal (Note 1) s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model > 200V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74VCX32374G (Note 2)(Note 3) Package Number BGA96A Package Descriptions 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 2: Ordering code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation
DS500402
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74VCX32374
Connection Diagram
Pin Descriptions
Pin Names OEn CPn I0–I31 O0–O31 Description Output Enable Input (Active LOW) Clock Pulse Input Inputs Outputs
FBGA Pin Assignments
1 A B C D E F G H (Top Thru View) J K L M N P R T O1 O3 O5 O7 O9 O11 O13 O14 O17 O19 O21 O23 O25 O27 O29 O30 2 O0 O2 O4 O6 O8 O10 O12 O15 O16 O18 O20 O22 O24 O26 O28 O31 3 OE1 GND VCC GND GND VCC GND OE2 OE3 GND VCC GND GND VCC GND OE4 4 CP1 GND VCC GND GND VCC GND CP2 CP3 GND VCC GND GND VCC GND CP4 5 I0 I2 I4 I6 I8 I10 I12 I15 I16 I18 I20 I22 I24 I26 I28 I31 6 I1 I3 I5 I7 I9 I11 I13 I14 I17 I19 I21 I23 I25 I27 I29 I30
Truth Tables
Inputs CP1 Outputs I0–I7 H L X X O0–O7 H L O0 Z CP2 Inputs Outputs I8–I15 H L X X O8–O15 H L O0 Z
L X
OE1 L L L H
L X
OE2 L L L H
Inputs CP3
Outputs I16–I23 H L X X O16–O23 H L O0 Z CP4
Inputs
Outputs I24–I31 H L X X O24–O31 H L O0 Z
L X
OE3 L L L H
L X
OE4 L L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP
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74VCX32374
Functional Description
The 74VCX32374 consists of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 32-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VCX32374
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATED Outputs Active (Note 5) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
−0.5V to +4.6V −0.5V to +4.6V −0.5V to +4.6V −0.5V to VCC +0.5V −50 mA −50 mA +50 mA ±50 mA ±100 mA −65°C to +150 °C
Recommended Operating Conditions (Note 6)
Power Supply Operating Input Voltage Output Voltage (VO) Output in Active States Output in 3-STATE Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V VCC = 1.4V to 1.6V VCC = 1.2V Free Air Operating Temperature (TA) Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 4: The Absolute Maximum Ratings are those valu.