74LVQ86

® 74LVQ86 QUAD EXCLUSIVE OR GATE s s s s s s s s s s s HIGH SPEED: tPD = 5.5 ns (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 86 IMPROVED LATCH-UP IMMUNITY M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVQ86M 74LVQ86T sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. DESCRIPTION The LVQ86 is a low voltage CMOS QUAD EXCLUSIVE OR GATE fabricated with PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/8 74LVQ86 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCT ION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L L H H B L H L H Y L H H L ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Ts...