74LVQ00

74LVQ00 Low Voltage Quad 2-Input NAND Gate LVQ00 November 1997 74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description The LVQ00 contains four 2-input NAND gates. Features n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω Ordering Code: Order Number 74LVQ00SC 74LVQ00SJ See Package Description 14-Lead (0.150" Wide) Molded Small Outline Integrated Circuit, SOIC JEDEC 14-Lead Small Outline Package, SOIC EIAJ Package Number M14A M14D Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Assignment for for SOIC JEDEC and EIAJ DS011341-1 DS011341-2 Pin Descriptions Pin Names An, Bn On Description Inputs Outputs © 1997 Fairchild Semiconductor Corporation DS011341 www.fairchildsemi.com 1 PrintDate=1997/11/10 PrintTime=09:36:39 23554 ds011341 Rev. No. 4 cmserv Proof 1 Absolute Maximum Ratings Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current (Note 1) −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0...