74LVCH32373A

INTEGRATED CIRCUITS DATA SHEET 74LVCH32373A 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state Product specification File under Integrated Circuits, IC24 1999 Nov 24 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state FEATURES 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 to 3.6 V CMOS low power consumption MULTIBYTE™ flow-trough standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Bus hold on data inputs Typical output ground bounce voltage: VOLP < 0.8 V at VCC = 3.3 V and Tamb = 25 °C Typical output undershoot voltage: VOHV > 2 V at VCC = 3.3 V and Tamb = 25 °C Power off disables outputs, permitting live insertion Packaged in plastic fine-pitch ball grid array package. DESCRIPTION The 74LVCH32373A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 or 5 V environment. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPHL/tPLH PARAMETER propagation delay nDn to nQn nLE to nQn CI CPD Note 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2...