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MG65P Dataheets PDF



Part Number MG65P
Manufacturers OKI electronic componets
Logo OKI electronic componets
Description 0.25m Embedded DRAM/ Customer Structured Arrays
Datasheet MG65P DatasheetMG65P Datasheet (PDF)

DATA SHEET O K I A S I C P R O D U C T S MG63P/64P/65P 0.25µm Embedded DRAM/ Customer Structured Arrays November 1998 MG63P/64P/65P 0.25µm Embedded DRAM/Customer Structured Arrays DESCRIPTION Oki’s 0.25 µm MG63P/64P/65P Application-Specific Integrated Circuit (ASIC) provides the ability to embed large blocks of Synchronous DRAM (SDRAM) into an embedded array architecture called the Customer Structured Array (CSA). Utilizing Oki’s leadership in DRAM technologies and wide experience of embedding.

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DATA SHEET O K I A S I C P R O D U C T S MG63P/64P/65P 0.25µm Embedded DRAM/ Customer Structured Arrays November 1998 MG63P/64P/65P 0.25µm Embedded DRAM/Customer Structured Arrays DESCRIPTION Oki’s 0.25 µm MG63P/64P/65P Application-Specific Integrated Circuit (ASIC) provides the ability to embed large blocks of Synchronous DRAM (SDRAM) into an embedded array architecture called the Customer Structured Array (CSA). Utilizing Oki’s leadership in DRAM technologies and wide experience of embedding SDRAM in logic products, Oki is able to integrate SDRAM and ASIC technology. The merged DRAM/ASIC process efficiently implements the Oki stacked capacitor memory cell. The MG63P/64P/65P CSA series uses three, four, and five metal process layers, respectively, on 0.25 µm drawn (0.18 µm L-effective) CMOS technology. The semiconductor process is adapted from Oki’s production-proven 64- Mbit DRAM manufacturing process. The 0.25 µm family provides significant performance, density, and power improvement over previous 0.30 µm and 0.35 µm technologies. An innovative 4-transistor cell structure provides 30 to 50% less power and 30 to 50% more usable gates than traditional cell designs. The Oki 0.25 µm family operates using 2.5-V VDD core with optimized 3-V I/O buffers. The 3-, 4-, and 5-layer metal MG63P/64P/65P CSA series contains 21 devices each, offering up to 868 I/O pads and over 5.4M raw gates. These CSA array sizes are designed to fit the most popular quad flat pack (QFP), low profile QFPs (LQFPs), thin QFPs (TQFPs), and plastic ball grid array (PBGA) packages. Oki uses the Artisan Components memory compiler which provides high performance, embedded synchronous single- and dual-port SRAM macrocells for CSA designs. As such, the MG63P/64P/65P series is suited to memory-intensive ASICs and high volume designs where fine tuning of package size produces significant cost or real-estate savings. The embedded SDRAM represents part of Oki’s menu of major IP core functions for the 0.25 µm ASIC products. Other functions include ARM7TDMI, Gb Ethernet MAC, PLL, PCI and others in planning. FEATURES • • • • • • 0.25µm drawn 3-, 4-, and 5-layer metal CMOS Optimized 2.5-V core Optimized 3-V I/O CSA architecture availability 100 MHz embedded SDRAM cores up to 16 Mb per occurrence 77-ps typical logic gate propagation delay (for a 4x-drive inverter gate with a fanout of 2 and 0 mm of wire, operating at 2.5 V) Over 5.4M raw gates and 868 I/O pads using 60µ staggered I/O User-configurable I/O with VSS, VDD, TTL, 3-state, and 1- to 24-mA options Slew-rate-controlled outputs for low-radiated noise H-clock tree cells which reduces the maximum skew for clock signals • Low 0.2µW/MHz/gate power dissipation • User-configurable single- and dual-port memories (SRAM) • Specialized IP cores and macrocells including 32-bit ARM7TDMI CPU, phase-locked loop (PLL), and peripheral component interconnect (PCI) cells • Floorplanning for front-end simulation, backend layout controls, and link to synthesis • Joint Test Action Group (JTAG) boundary scan and scan path Automatic Test Pattern Generation (ATPG) • Support for popular CAE systems including Cadence, IKOS, Mentor Graphics, Model Technology, Inc. (MTI), Synopsys, and Viewlogic • • • • Oki Semiconductor 1 s MG63P/64P/65P s –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– MG63P/64P/65P FAMILY LISTING Series (MG6x) B02 B04 B06 B08 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 B30 B32 B34 B36 B38 B40 B42 No. of Pads 68 108 148 188 228 268 308 348 388 428 468 508 548 588 628 668 708 748 788 828 868 No. of Rows 84 144 204 264 324 384 444 504 564 624 684 744 804 864 924 984 1,044 1,104 1,164 1,224 1,284 No. of Columns 280 480 680 880 1,080 1,280 1,480 1,680 1,880 2,080 2,280 2,480 2,680 2,880 3,080 3,280 3,480 3,680 3,880 4,080 4,280 No. of Raw Gates 23,520 69,120 138,720 232,320 349,920 491,520 657,120 846,720 1,060,320 1,297,920 1,559,920 1,845,120 2,154,720 2,488,320 2,845,920 3,227,520 3,633,120 4,062,720 4,516,320 4,993,920 5,495,520 MG63P 3LM Usable Gates 20,933 57,370 106,814 167,270 234,446 309,658 387,701 474,163 572,573 648,960 732,974 848,755 969,624 1,094,861 1,223,746 1,355,558 1,489,579 1,625,088 1,761,365 1,897,690 2,033,342 MG64P 4LM Usable Gates 22,344 65,664 131,784 218,381 311,429 412,877 519,125 635,040 763,430 882,586 982,498 1,107,072 1,249,738 1,393,459 1,536,797 1,678,310 1,816,560 1,950,106 2,077,507 2,197,325 2,308,118 MG65P 5LM Usable Gates 22,344 65,664 131,784 220,704 332,424 466,944 611,122 745,114 901,272 1,025,357 1,154,045 1,310,035 1,465,210 1,642,291 1,821,389 2,001,062 2,179,872 2,356,378 2,529,139 2,696,717 2,857,670 5 layer metal: MG65PBxx 4 layer metal: MG64PBxx 3 layer metal: MG63PBxx ARRAY ARCHITECTURE The primary components of a 0.25µm MG63P/64P/65P circuit include: • • • • • • • • I/O base cells 60µm pad pitch Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O) VDD and VSS pads dedicated to wafer probing Separate power bus f.


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