MD56V62800A

E2G1054-18-62 ¡ Semiconductor MD56V62800A ¡ Semiconductor This version: Jun. 1998 MD56V62800A Pr el im in ar y 4-Bank ¥ 2,097,152-Word ¥ 8-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MD56V62800A is a 4-bank ¥ 2,097,152-word ¥ 8-bit synchronous dynamic RAM, fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 4-bank ¥ 2,097,152-word ¥ 8-bit configuration 3.3 V power supply, ± 0.3 V tolerance Input : LVTTL compatible Output : LVTTL compatible Refresh : 4096 cycles/64 ms Programmable data transfer mode – CAS latency (1, 2, 3) – Burst length (1, 2, 4, 8, full page) – Data scramble (sequential, interleave) Burst read single bit write capability CBR auto-refresh, Self-refresh capability Package: 54-pin 400 mil plastic TSOP (Type II) (TSOPII54-P-400-0.80-K) (Product : MD56V62800A-xxTA) xx indicates speed rank. PRODUCT FAMILY Family MD56V62800A-8 MD56V62800A-10 Max. Frequency 125 MHz 100 MHz Access Time (Max.) tAC2 10 ns 9 ns tAC3 6 ns 9 ns 1/28 ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) VCC DQ1 VCCQ NC DQ2 VSSQ NC DQ3 VCCQ NC DQ4 VSSQ NC VCC NC WE CAS RAS CS A13/BA0 A12/BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 MD56V62800A   10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 VSS 53 DQ8 52 VSSQ 51 NC 50 DQ7 49 VCCQ 48 NC 47 DQ6 46 VSSQ 45 NC 44 DQ5 43 VCCQ 42 NC 41 VSS 40 NC 39 DQM 38 CLK ...