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PI6C2516 Dataheets PDF



Part Number PI6C2516
Manufacturers Pericom Semiconductor Corporation
Logo Pericom Semiconductor Corporation
Description Phase-Locked Loop Clock Driver with 16 Clock Outputs
Datasheet PI6C2516 DatasheetPI6C2516 Datasheet (PDF)

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  PI6C2516   PI6C2516


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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs Product Features • High Performance Phase-Locked Loop Clock Distribution for Synchronous DRAM, server and networking applications. • Zero Input-to-Output delay: Distribute One Clock Input to four banks of four outputs, with separate output enables for each bank. • Allow Clock Input to have Spread Spectrum modulation for EMI reduction. The clock outputs track the Clock Input modulation. • Maximum clock frequency of 150 MHz. • Low jitter: Cycle-to-Cycle jitter ±100ps max • Operates at 3.3V VCC • Available Packaging: – 48-pin TSSOP (Thin Shrink Small Outline) (A) Description The PI6C2516 family is a low-skew, low jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM, server and networking applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK input to any clock output will be nearly zero. This zero-delay feature allows the CLK input clock to be distributed, providing 4 banks of four outputs. For test purposes, the PLL can be bypassed by strapping the AVCC to ground. The PI6C2516 family has the same pinout as the TI CDC2516, with the added feature of allowing Spread Spectrum clock input. Pin Description VCC 1Y0 1Y1 GND GND 1Y2 1Y3 VCC 1G GND AVCC CLK AGND AGND GND 2G VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 48-Pin 39 11 A 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 VCC 4Y0 4Y1 GND GND 4Y2 4Y3 VCC 4G GND AVCC FB_IN AGND FB_OUT GND 3G VCC 3Y0 3Y1 GND GND 3Y2 3Y3 VCC Block Diagram 1G 2G 3G 4G 4 4 4 1Y [0:3] 2Y [0:3] 3Y [0:3] CLK PLL FB_IN AVCC 4 4Y [0:3] FB_OUT 1 PS8440C 07/24/01 PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Functions Pin Name CLK FB_IN Pin Numbe r 12 37 Type I I D e s cription Clock input. CLK allows spread spectrum. Feedback input. FB_IN provides the feedback signal to the internal PLL. CLK ↑ and FB_IN↑ are synchronized so that there is normally zero phase error between CLK and FB_IN. O utput bank enable. When 1G is LO W, outputs 1Y[0:3] are disabled to a logic low state. When 1G is HIGH, all outputs 1Y[0:3] are enabled and switched at the same frequency as CLK . O utput bank enable. When 2G is LO W, outputs 2Y[0:3] are disabled to a logic low state. When 2G is HIGH, all outputs 2Y[0:3] are enabled and switched at the same frequency as CLK . O utput bank enable. When 3G is LO W, outputs 3Y[0:3] are disabled to a logic low state. When 3G is HIGH, all outputs 3Y[0:3] are enabled and switched at the same frequency as CLK . O utput bank enable. When 4G is LO W, outputs 4Y[0:3] are disabled to a logic low state. When 4G is HIGH, all outputs 4Y[0:3] are enabled and switched at the same frequency as CLK . Feedback output. FB_O UT is dedicated for external feedback. FB_O UT has an embedded 25Ω series- damping resistor of the same value as the clock outputs. Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25Ω series- damping resistor of the same value as the clock outputs. Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25Ω series- damping resistor of the same value as the clock outputs. Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25Ω series- damping resistor of the same value as the clock outputs. Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25Ω series- damping resistor of the same value as the clock outputs. Analog power supply. AVCC can be also used to bypass the PLL for test purposes. When AVC C is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. 1G 9 I 2G 16 I 3G 33 I 4G FB_O UT 1Y[0:3] 40 35 2,3,6,7 I O O 2Y[0:3] 18,19,22,23 O 3Y[0:3] 26,27,30,31 O 4Y[0:3] 42,43,46,47 O AVCC AGND VC C GND 11,38 13,14,36 1,8,17,24,25,32,41,48 4,5,10,15,20,21,28,29, 34,39,44,45 Power Ground Analog ground. AGND provides the ground reference for the analog circuitry. Power Power supply Ground Ground 2 PS8440C 07/24/01 PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567.


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