Philips Semiconductors
Objective Specification
PowerMOS transistor Isolated version fo PHP1N50E
GENERAL DESCRIPTION
N-...
Philips Semiconductors
Objective Specification
PowerMOS
transistor Isolated version fo PHP1N50E
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power
transistor in a full pack, plastic envelope featuring high avalanche energy capability, stable blocking voltage, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications.
PHX1N50E
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance MAX. 500 1.4 25 5 UNIT V A W Ω
PINNING - SOT186A
PIN 1 2 3 gate drain source DESCRIPTION
PIN CONFIGURATION
case
SYMBOL
d
g
case isolated
1 2 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDS VDGR ±VGS ID IDM IDR IDRM Ptot Tstg Tj Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (pulse peak value) Source-drain diode current (DC) Source-drain diode current (pulse peak value) Total power dissipation Storage temperature Junction temperature CONDITIONS RGS = 20 kΩ Ths = 25 ˚C Ths = 100 ˚C Ths = 25 ˚C Ths = 25 ˚C Ths = 25 ˚C Ths = 25 ˚C MIN. -55 MAX. 500 500 30 1.4 0.9 5.6 1.4 5.6 25 150 150 UNIT V V V A A A A A W ˚C ˚C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER WDSS CONDITIONS MIN. MAX. UNIT Drain-source non-repetitive ID = 2 A ; VD...