Document
Philips Semiconductors
Objective specification
PowerMOS transistor
PHT1N52S
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic envelope suitable for surface mounting featuring high avalanche energy capability, stable blocking voltage, fast switching and high thermal cycling performance. Intended for use in Compact Fluorescent Lights (CFL) and general purpose switching applications.
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance MAX. 520 0.6 1.8 10 UNIT V A W Ω
PINNING - SOT223
PIN 1 2 3 4 gate drain source drain (tab) DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
d
g
1
2
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDS VDGR ±VGS ID IDM IDR IDRM Ptot Tstg Tj Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (pulse peak value) Source-drain diode current (DC) Source-drain diode current (pulse peak value) Total power dissipation Storage temperature Junction temperature CONDITIONS RGS = 20 kΩ Tsp = 25 ˚C Tsp = 100 ˚C Tsp = 25 ˚C Tsp = 25 ˚C Tsp = 25 ˚C Tsp = 25 ˚C MIN. -55 MAX. 520 520 30 0.6 0.5 2.4 0.6 2.4 1.8 150 150 UNIT V V V A A A A A W ˚C ˚C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER WDSS CONDITIONS MIN. MAX. UNIT Drain-source non-repetitive ID = 1 A ; VDD ≤ 50 V ; VGS = 10 V ; unclamped inductive turn-off RGS = 50 Ω energy Tj = 25˚C prior to surge Tj = 100˚C prior to surge Drain-source repetitive ID = 1 A ; VDD ≤ 50 V ; VGS = 10 V ; unclamped inductive turn-off RGS = 50 Ω ; Tj ≤ 150 ˚C energy
WDSR1
-
25 10 3.6
mJ mJ mJ
1. Pulse width and frequency limited by Tj(max)
February 1998
1
Rev 1.000
Philips Semiconductors
Objective specification
PowerMOS transistor
PHT1N52S
THERMAL RESISTANCES
SYMBOL Rth j-sp Rth j-a PARAMETER Thermal resistance junction to solder point Thermal resistance junction to ambient CONDITIONS MIN. pcb mounted; minimum footprint pcb mounted; pad area as in fig:2 TYP. 156 70 MAX. 15 UNIT K/W K/W K/W
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS RDS(ON) VSD PARAMETER Drain-source breakdown voltage Gate threshold voltage Drain-source leakage current Gate-source leakage current Drain-source on-state resistance Source-drain diode forward voltage CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA VDS = 500 V; VGS = 0 V; Tj = 25 ˚C VDS = 400 V; VGS = 0 V; Tj = 125 ˚C VGS = ±35 V; VDS = 0 V VGS = 10 V; ID = 1 A IF = 2 A ;VGS = 0 V MIN. 520 2.0 TYP. 3.0 1 0.1 4 7.9 0.85 MAX. 4.0 100 1.0 100 10 1.2 UNIT V V µA mA nA Ω V
DYNAMIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified SYMBOL gfs Ciss Coss Crss Qg(tot) Qgs Qgd td on tr td off tf trr Qrr PARAMETER Forward transconductance Input capacitance Output capacitance Feedback capacitance Total gate charge Gate to source charge Gate to drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Source-drain diode Reverse recovery time Source-drain diode Reverse recovery charge CONDITIONS VDS = 15 V; ID = 1 A VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. 0.5 TYP. 0.8 75 10 5 5 .5 3 5 15 15 7 150 1.5 MAX. 100 15 10 10 20 20 15 UNIT S pF pF pF nC nC nC ns ns ns ns ns µC
VGS = 10 V; ID = 2 A; VDS = 400 V
VDD = 30 V; ID = 2 A; VGS = 10 V; RGS = 50 Ω; RGEN = 50 Ω IF = 2 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 100 V
February 1998
2
Rev 1.000
Philips Semiconductors
Objective specification
PowerMOS transistor
PHT1N52S
MOUNTING INSTRUCTIONS
Dimensions in mm.
3.8 min
1.5 min
2.3 1.5 min (3x)
6.3
1.5 min
4.6
Fig.1. soldering pattern for surface mounting SOT223.
PRINTED CIRCUIT BOARD
Dimensions in mm.
36
18
60 9 4.6 4.5
10
7 15 50
Fig.2. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick).
February 1998
3
Rev 1.000
Philips Semiconductors
Objective specification
PowerMOS transistor
PHT1N52S
MECHANICAL DATA
Dimensions in mm Net Mass: 0.11 g
0.32 0.24 6.7 6.3 3.1 2.9 B 0.2 M A
4
A
0.10 0.02
3.7 3.3 13
7.3 6.7
16 max
1
10 max 1.8 max 1.05 0.85 4.6 2.3
2
0.80 0.60
3
0.1 M (4x) B
Fig.3. SOT223 surface mounting package.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to surface mounting instructions for SOT223 envelope. 3. Epoxy meets UL94 V0 at 1/8".
February 1998
4
Rev 1.000
Philips Semiconductors
Objective specification
PowerMOS transistor
PHT1N52S
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at .