Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
FEATURES
• ’Trench’ technology • Ve...
Philips Semiconductors
Product specification
TrenchMOS™
transistor Logic level FET
FEATURES
’Trench’ technology Very low on-state resistance Fast switching Stable off-state characteristics High thermal cycling performance Low thermal resistance
PHP125N06LT, PHB125N06LT
SYMBOL
d
QUICK REFERENCE DATA VDSS = 55 V ID = 75 A
g s
RDS(ON) ≤ 8 mΩ (VGS = 5 V) RDS(ON) ≤ 7 mΩ (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power
transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP125N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB125N06LT is supplied in the SOT404 surface mounting package.
PINNING
PIN 1 2 3 tab gate drain 1 source drain DESCRIPTION
SOT78 (TO220AB)
tab
SOT404
tab
2
1 23
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 55 55 ± 13 75 75 240 250 175 UNIT V V V A A A W ˚C
March 1998
1
Rev 1.400
Philips Semiconductors
Product specification
Tre...