MACH211SP-7

FINAL COM’L: -7.5/10/12/15/20 IND: -10/12/14/18/24 MACH211SP-7/10/12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s JTAG-Compatible, 5-V in-system programming s 44 Pins s 64 Macrocells s 7.5 ns tPD Commercial 10 ns tPD Industrial s 133 MHz fCNT s 34 Bus-Friendly™ Inputs and I/Os s Peripheral Component Interconnect (PCI) compliant (-7/-10) s Programmable power-down mode s s s s 32 Outputs 64 Flip-flops; 2 clock choices 4 “PAL26V16” blocks with buried macrocells Improved routing over the MACH210 IN-SYSTEM PROGRAMMING In-system programming allows the MACH211SP to be programmed while soldered onto a system board. Programming the MACH211SP in-system yields numerous benefits at all stages of development: prototyping, manufacturing, and in the field. Since insertion into a programmer isn’t needed, multiple handling steps and the resulting bent leads are eliminated. The design can be modified in-system for design changes and debugging while prototyping, programming boards in production, and field upgrades. The MACH211SP offers advantages not available in other CPLD architectures with in-system programming. MACH devices have extensive routing resources for pin-out retention; design changes resulting in pin-out changes for other CPLDs cancel the advantages of in-system programming. The MACH211SP can be employed in any JTAG (IEEE 1149.1) compliant chain. GENERAL DESCRIPTION The MACH211SP is a member of AMD’s EE CMOS Performance Plus MACH® 2 device family. Th...